Physical design for high-performance designs going into industry leading CPU and AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside with a group of highly experienced engineers across various domains of the CPU/AI chip.

This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Ft. Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Discussions with 3rd party IP providers, foundry partners and design services
• End to end tasks from flow development to sign-off
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

• BS/MS/PhD in EE/ECE/CE/CS
• Minimum BS and 10+ years of experience in Physical Design
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Strong programming skills in Tcl/Perl/Shell/Python
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Exposure to DFT is an asset
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong problem solving and debug skills across various levels of design hierarchies