Full-Time
ASIC Engineer
Updated on 9/4/2026
Jobsbridge
No salary listed
San Jose, CA, USA
In Person
Category
 Hardware Engineering (1) |
|---|
Required Skills
Verilog
VHDL
FPGA
Requirements
- At least 2 years of experience in FPGA or ASIC development.
- Experience with ASIC design, FPGA, RTL design, chip architecture, ASIC implementation, synthesis, and Conformal formal verification using Cadence tools.
- Ability to build RTL designs of digital circuits using VHDL and SystemVerilog.
- Ability to perform frontend design development and integration of large ASIC designs.
- Ability to collaborate with Chip Architecture, Design Verification, and Physical Design teams.
- Ability to write design documents, including high-level interface descriptions and design descriptions.
- Ability to write functional test cases and test benches to verify design functionality.
Responsibilities
- Build RTL designs of digital circuits using VHDL and SystemVerilog.
- Perform frontend design development and integration of large ASIC designs.
- Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.
- Write design documents including high-level interface descriptions and design descriptions.
- Write functional test cases and test benches to verify design functionality.