As an FPGA Engineer in our mixed signal audio development team, you will perform the synthesis, place and route of ASIC designs on to FPGA platforms. You will bring up the design on the FPGA prototyping platform and ensure it can be used by other teams.

Responsibilities:

• Port ASIC RTL into FPGA-friendly RTL, taking it through synthesis and place & route.
• Develop RTL code to improve the ease of use of the ASIC design in the FPGA platform.
• Perform Static Timing Analysis on implemented designs.
• Bring up the design on FPGA prototyping platforms.
• Work with multi-functional teams to ensure they can use the FPGA platform and support them when facing problems.
• Define and run functional verification tests to prove the FPGA builds prior to FPGA distribution.
• Tests and debugs the emulation/FPGA model and collaterals.
• Validate new digital IP and architectures on FPGAs prior to silicon being produced.
• Develop automation tools and test to help improve the implementation and verification flows.

Required Skills and Qualifications

• Master’s degree in Electrical Engineering, Computer Science or similar subject area and 3+ years of directly related experience.
• Experience using FPGAs and an understanding of how FPGA design differs from ASIC design.
• Proficient in operating the simulation and modeling equipment including the design tools.
• Knowledge of Verilog, System Verilog and digital design concepts.
• Understanding of electronics on the bench with use of lab equipment such as oscilloscopes and logic analyzers.
• Verification/validation techniques and methodologies, including strong debugging skills.
• Experience with FPGA debug methodologies, tools (ChipScope), and lab debug equipment (oscilloscopes, logic analyzers).
• Understanding of common FPGA primitives such as memories, I/O pads, BUFG and MMCMs
• Familiar with common on-chip bus protocols such as AMBA (AXI, AHB, APB) and communication protocols such as SPI, I2C, I2S, UART.

Preferred Skills and Qualifications

• Have a curious and inquiring mind with the dedication to follow through on getting answers.
• Scripting knowledge (Python/Tcl) is desired.
• Experience in FPGA flows - Synthesis, P&R and Timing closure, with emphasis on Synopsys Synplify and Xilinx Vivado.
• Experience with Floorplanning and advanced timing closure techniques.
• Solid documentation, communication and interpersonal skills.
• Work to tight and variable time scales.
• Work independently as well as part of a team.
• Demonstrate excellent attention to detail.

This position is located in Austin, TX

This is a hybrid remote position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic. 

Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, genetic information or any other characteristic protected by law.