Principal Synthesis & Front-End STA Engineer
Posted on 10/27/2022
Redmond, WA, USA
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 10+ years of experience working as a synthesis and/or front-end STA engineer
- Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
- Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removal
- Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)
- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
- Deep understanding of ASIC design flow, top-down and bottom-up design methodologies
- Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
- Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
- Experience with high reliability design and implementations
- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
- Must be willing to travel when needed (typically <10%)
- To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here
- Full chip and block level timing constraint development, consistent full chip and block constraint partitioning
- Integrate DFT/BIST insertion flows into synthesis flow
- Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
- Analysis of clock domain crossing paths at block and full chip level
- Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
- Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows
- Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
- Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock domain crossing flows
- Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure
- Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs - generally bridging the RTL and place & route
- Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process
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