Senior ASIC Design Engineer

How You Will Contribute:

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for a hardworking digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a senior digital design engineer will be to propose innovative solutions, in order to craft power and area optimized functional blocks for the Wavelogic family of products.

• As lead digital design engineer, you are required to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects

• You will produce an implementation specification document and have it reviewed by your team, architects, analog designers if applicable

• You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions

• You are held responsible for designer testing of your code as well as debugging of your code during simulation and regression verification

• You will assist the verification team in resolving coverage and provide design assertions and waivers as needed

• You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews

• You will be involved in lab validation of the product and its prototype if applicable

• Reporting status updates on a regular basis

• Lead architecture and reviews of subsystems

• Lead top level architecture, RTL, and backend implementation.

• Guide subsystem and device implementation through to tapeout

• Responsible for interactions with and deliveries to and from 3rd party vendors

• Tracking issues to resolution

• Lead team where appropriate

The Must Haves:

• Expert-level experience (10 years +) with digital design synthesis, STA, timing closure and asynchronous clock crossing

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level

• A highly motivated self-starter, able to work independently, while being a great teammate

• Ability to methodically solve complex technical problems

• Excellent organization, written and oral (English) communication skills

• Proficiency above the intermediate level with use of System Verilog for design

• Familiarity with digital (including formal) verification methods

• Good understanding of timing/power/area analysis and trade-offs

The Assets:

• Experience with digital silicon design backend process

• Experience with digital design for low power

• Experience in DSP and/or Forward Error Correction

• Experience with standards and protocols such as OTN, B100G, Ethernet

• Experience with mixed-signal design

• Experience with using Jira for bug tracking and GIT for source code management and revision tracking

• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

Pay Range:

The annual salary range for this position in Ottawa is $109,000 - $174,000 CAD.

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