Responsibilities

• Build end to end simulation models for high speed interfaces (DDR/PCIE, etc), find solution path and design space, come up with routing rules, implement them in constraint manager files.
• Build end to end simulation models for power delivery network, evaluate Vdroop contribution from various components (VRM, PCB, socket, package, silicon etc), define PDN requirements, and come up with solution recommendations.
• Model extraction of all components: PCB, connectors, socket, package substrate, and drive silicon model extraction and validation.
• Define package and PCB stackup, material selection, decap selection, routing rule development.
• Work closely with package designers, PCB designers, EE, power engineers, thermal/mechanical engineers, package and PCB technologists to implement the designs, optimize for performance and perform sign off simulations.
• Validate bare substrate, PCB, socket, connector interconnect performance and PDN measurement in lab.    
• Fully involved in silicon and board bring up, functional and performance validation, debug triage, and compliance test.
• Contribute to SIPI methodology development, lab build up.

Requirements

• Use 3D modeling EDA tool to design and optimize passive channels. Knowledge of assessing channel quality and analyzing link defects.  
• Time domain simulation tools to do end-to-end eye diagram analysis.
• Lab validation and correlation using instruments such as Vector Network Analyzer.
• Knowledge of power delivery networks. PI modeling of various power supply modules, decaps, Vdroop budgeting, CPM model and current profile generation, validation.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.

Education and Experience

• PhD or Master’s Degree in EE or related fields with focus on SI and PI is preferred.