SIPI Intern
Confirmed live in the last 24 hours
Rivos

201-500 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.
Hardware

Company Stage

Series A

Total Funding

$120M

Founded

2021

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

0%

1 year growth

11%

2 year growth

40%
Locations
Santa Clara, CA, USA
Experience Level
Intern
Requirements
  • PhD or Master’s Degree in EE or related fields with focus on SI and PI
  • Experience in using 3D modeling EDA tool for designing and optimizing passive channels
  • Knowledge of assessing channel quality and analyzing link defects
  • Proficiency in time domain simulation tools for end-to-end eye diagram analysis
  • Experience in lab validation and correlation using instruments such as Vector Network Analyzer
  • Understanding of power delivery networks and PI modeling of various power supply modules, decaps, Vdroop budgeting, CPM model, and current profile generation
Responsibilities
  • Building end-to-end simulation models for high-speed interfaces and power delivery network
  • Model extraction of all components and validation
  • Defining package and PCB stackup, material selection, decap selection, and routing rule development
  • Working closely with package designers, PCB designers, EE, power engineers, thermal/mechanical engineers, package and PCB technologists
  • Validating bare substrate, PCB, socket, connector interconnect performance and PDN measurement in the lab
  • Involvement in silicon and board bring up, functional and performance validation, debug triage, and compliance test
  • Contributing to SIPI methodology development and lab build-up