Staff Formal Verification Engineer
Updated on 5/24/2023
Austin, TX, USA
Experience Level
  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  • Prior experience with formal verification methods and techniques
  • Strong knowledge of computer architecture with some experience on CPU, GPU, Cache designs
  • Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc
  • Proficiency in programing/scripting languages
  • Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator), experience capturing design specification in a temporal assertion language such as SVA
  • Strong problem solving and debug skills for complex logic and digital designs
  • Drive formal verification for multiple CPU blocks by putting together formal test plans and executing on them
  • Create formal verification flows and deploy techniques that leverage on both industry standard and open-source tools. Drive automation of formal testbenches and ensure they are a part of regressions
  • Develop assertions, cover properties and connectivity checks as a part of formal verification flows and debug any failures in RTL regressions
  • Deploy scripts and automation to support formal, review setups and proofs with Microarchitecture and DV engineers

51-200 employees

Computer processor architecture manufacturer
Company Overview
Tenstorrent is on a mission to address the rapidly growing compute demands for software 2.0. The company designs processors that are optimized for neural network inference, training and can also execute other types of parallel computation.
Company Core Values
  • Collaboration
  • Curiosity
  • Commitment to solving hard problems