Design for Testability
Dft, Architect
Posted on 4/22/2022
INACTIVE
Aeva

201-500 employees

Sensing & perception for autonomous machines
Company Overview
Aeva's mission is to enable all devices to navigate the world autonomously. Aeva envisions its technology as part of everyday life, and are making this a reality by developing the world’s most advanced LIDAR on the market.
Data & Analytics
Automotive & Transportation
Hardware

Company Stage

N/A

Total Funding

$368.5M

Founded

2017

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

7%

1 year growth

24%

2 year growth

33%
Locations
Mountain View, CA, USA
Experience Level
Entry
Junior
Mid
Senior
Expert
Requirements
  • 2-5 years' experience writing RTL code in Verilog and/or VHDL
  • 2-5 years of verification experience
  • Broad domain knowledge of DFT including Scan/ATPG, MBiST, LBiST, JTAG, TAP, IO BiST, Analog BiST, etc
  • In depth knowledge of EDA tools used in DFT
  • Lab debug and DFT bringup experience
  • Ability to deliver results in a very fast-moving environment
  • Desire to learn & implement groundbreaking new hardware technology
  • Excellent communication and organization skills
Responsibilities
  • As an SoC DFT Architect you'll be responsible for defining and/or overseeing, advanced design-for-test (DFT) methodologies for highly-complex digital and/or mixed-signal chips and/or IPs. You will have the opportunity to work with the rest of the team to document DFT specifications, and also develop DFT methodologies and infrastructure. In this role, you'll oversee the definition, development and verification of a consistent methodology for DFT across the whole SoC
Desired Qualifications
  • Functional Safety Experience