Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
Job Description
We are looking for a hands-on Senior Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team that will deliver micro-architecture and implementation of the front-end digital design, including RTL, synthesis, IP integration, and block-level verification for high performance ASICs. The candidate must have good knowledge of communication/interface protocols such as CXL/PCIE (Gen-3 and above) or Ethernet.
Basic qualifications:
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
- 15+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- 10+ years’ experience managing a team of RTL design engineers.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in US and start immediately.
Required experience:
- Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe or Ethernet.
- Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
- Experience with Cadence and/or Synopsys digital design tools/flows
- Experience with scripting and automation, with a strong methodology background.
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
- Familiarity with UVM based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (≤28nm) design
Preferred experience:
- Scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
The base salary range is USD 192,000.00 USD – USD 260,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
