2023 Research Intern
Mixed-Signal/RFIC Design
Confirmed live in the last 24 hours
Locations
Plano, TX, USA
Experience Level
Intern
Desired Skills
Communications
Verilog
Requirements
- MSEE or PhD student preferable or equivalent combination of education, training, and experience
- Successful tape-out experience are preferred on the mixed-signal/RF IC in CMOS (below 65nm) such as high speed pipeline ADC, time-interleaved SAR ADC, PLL and RF frond end
- Strong understanding of the mixed-signal blocks and its related simulation techniques
- Strong understanding of RF circuits design fundamentals and RF communication architectures
- Proficient using Cadence and Verilog AMS. Experience with HFSS and Momentum will help
- Strong debugging and analytical skills
- Works well with others and can brainstorm potential solutions together
Responsibilities
- Work with senior Samsung Engineers to develop new circuit building blocks and ideas
- Design, layout and post-layout verification of related blocks
- Optimize circuit to meet the specifications for system performance
- Validate performance of circuits, modules, and systems using standard test equipment such as spectrum analyzers, network analyzers, VSA
- Prepare the design and measurement documents
The American arm of the R&D hub of Samsung Electronics
Company Overview
SRA is on a mission to create superior products and services that contribute to a better global society. SRA is the American arm of the R&D hub for Samsung Electronics.
Benefits
- Onsite Fitness Facility
- Subsidized Meals
- Coffee Barista Bar
- Samsung University
- Product Discounts
- Dog Friendly Campus
- Wellness Programs
- Activity Clubs
Company Core Values
- People
- Excellence
- Change
- Integrity
- Co-Prosperity