Fabric/Interconnect Architect
Posted on 3/22/2024
Rivos

201-500 employees

High performance CPUs & RISC-V
Company Overview
Rivos is a startup in stealth-mode.
Hardware

Company Stage

Series A

Total Funding

$120M

Founded

2021

Headquarters

Mountain View, California

Growth & Insights
Headcount

6 month growth

1%

1 year growth

9%

2 year growth

41%
Locations
Austin, TX, USA • Santa Clara, CA, USA • Fort Collins, CO, USA • Portland...
Experience Level
Entry
Junior
Mid
Senior
Expert
Desired Skills
Verilog
Python
CategoriesNew
Hardware Engineering
Computer Hardware Engineering
Electronic Hardware Engineering
System Hardware Engineering
Requirements
  • Thorough knowledge of large scale on-chip fabric or on-chip interconnect architecture
  • Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.
  • Knowledge of cache coherent memory systems and interconnect.
  • Familiarity with different on-chip network topologies (ring, mesh, xbar etc).
  • Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as Python
  • Experience with functional and performance simulators
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power architecture techniques
  • Understanding of high performance techniques and trade-offs in fabric architecture
Responsibilities
  • Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specification
  • Coherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth and latency targets
  • Development, assessment, and refinement of Architecture to target power, performance, area, and timing goals
  • Helping produce and review validation plans for functionality and performance