Full-Time

DFT Engineer

Confirmed live in the last 24 hours

Rivos

Rivos

201-500 employees

High performance RISC-V computing solutions

Hardware

Mid

Austin, TX, USA + 3 more

Required Skills
Verilog
Python
Requirements
  • Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
  • Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
  • Knowledge of Verilog and experience with simulators and waveform debugging tools
  • Knowledge of Verilog / SystemVerilog
  • Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
  • Ability to work well in a team and be productive under aggressive schedules
Responsibilities
  • Define DFT strategy and methodologies
  • Design the DFT features
  • Define test structures, debug structures, and test plans
  • Create test vectors or oversee their creation
  • Collaborate with physical design team to close requirements
  • Validate DFT requirements are being met
  • Work with designers to increase test coverage, debug observability and flexibility
  • Verify post-PD designs meet DFT requirements
  • Work with verification engineers, stepping in to do run tests when needed

Rivos provides a compelling work environment for those keen on contributing to leading-edge computing solutions in the enterprise sector. The company is a specialist in leveraging high-performance RISC-V systems, positioning it as a key player in the advanced computing niche. Working here exposes employees to cutting-edge technology and significant industry challenges, nurturing a culture of innovation and technical excellence.

Company Stage

Series A

Total Funding

$250M

Headquarters

Santa Clara, California

Founded

2021

Growth & Insights
Headcount

6 month growth

4%

1 year growth

0%

2 year growth

47%