Overview
Vertical Compute develops chiplet-based technology that vertically integrates memory and compute to address the AI memory wall. It stacks high-aspect-ratio vertical data lanes above compute units, so data moves over nanometres instead of across long traces, improving energy use, density, and performance for AI at the edge. The company differentiates itself by co-designing memory and compute in a vertical chiplet stack to achieve higher density and lower data-transfer energy than traditional DRAM approaches, with a focus on privacy-preserving edge AI. Its goal is to move from seed funding to commercialization by building its engineering team and bringing its vertical memory-compute technology to market.
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Simplify's take
What believers are saying
- March 4, 2026, Vertical Compute raised €57 million, extending seed financing for R&D.
- Nov. 10, 2026, NanoIC pilot-line access de-risks manufacturing and speeds commercialization.
- July 2026 Lam finalist status widened visibility with semiconductor investors and potential partners.
What critics are saying
- No volume-production timetable or named foundry exists, exposing execution risk beyond 16nm.
- Memory-on-logic must beat entrenched DRAM, HBM, and advanced chiplet incumbents on cost.
- If 16nm integration fails, investor enthusiasm collapses and Europe’s VIM thesis stalls.
What makes Vertical Compute unique
- Nov. 10, 2026, imec partnership pushes VIM from validation to 16nm preproduction.
- Vertical columns place memory above logic, shrinking data movement from centimeters to nanometers.
- The 2024 imec spin-off combines magnetic memory with standard CMOS and pilot-line access.
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