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MatX

Designs high-throughput AI hardware chips

SOC Integration Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeMountain View, CA, USAHybrid

About the Job

Requirements

  • Demonstrate proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows.
  • Possess a proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOC RTL.
  • Apply working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL.
  • Manage memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL.
  • Provide automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes.
  • Leverage hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams.
  • Utilize hands-on experience with design synthesis, linting, clock and reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off.

Responsibilities

  • Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all subsystems into a comprehensive full-chip SOC RTL design.
  • Partner with subsystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) top-level RTL.
  • Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL.
  • Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL.
  • Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams.
  • Define and support SoC-level timing constraints, ensuring rigorous validation against subsystem design and physical design requirements.
  • Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists.

Desired Qualifications

  • Familiarity with emulation platforms and verification methodologies.

About the Company

MatX

Designs high-throughput AI hardware chips

MatX builds high-throughput AI accelerators for large language models. Its main product is a dedicated chip where every transistor is optimized for running large neural networks, aiming to deliver strong performance for training and inference of LLMs. The company also develops the surrounding software stack, including compilers, to make the hardware easy to program for ML engineers (e.g., through JAX-based workflows). Unlike general-purpose processors, MatX focuses on specialization and full-stack optimization from silicon to software. Its goal is to enable organizations with substantial AI workloads to scale efficiently by providing powerful, purpose-built hardware and the compatible software tools they need to deploy and optimize large models.

Company size
51-200
Company stage
Series B
Total funding
$604.9M
Headquarters
Mountain View, CA
Founded
2022

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