Senior Design-for-Test Engineer

WHAT YOU WILL BE DOING:

• Define and implement end-to-end DFT architecture and strategy for complex SoC designs, including scan, MBIST, BIST, and JTAG/IEEE 1149.x

• Insert and verify scan chains, compression logic, and test wrappers using industry-standard DFT tools

• Own the full ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up

• Perform fault simulation and analyze test coverage metrics to meet manufacturing test requirements

• Collaborate with physical design teams to optimize scan chain ordering, routing, and test timing

• Define and implement memory BIST (MBIST) and logic BIST (LBIST) strategies for embedded memories

• Work with ATE teams to develop test programs and validate tester compatibility

• Develop DFT automation scripts and integrate DFT flows into the overall design implementation flow

• Perform DFT sign-off verification and resolve DRC/functional issues related to DFT logic

• Document DFT specifications, methodology guidelines, and test coverage reports

WHAT YOU BRING TO THIS ROLE:

• MS/PhD or equivalent experience in Electrical Engineering or a related field

• Minimum 8+ years of hands-on experience in Design-for-Test (DFT) for complex digital ASICs or SoCs

• Hands-on experience with industry-standard DFT tools such as Synopsys DFT Compiler, Tessent, or equivalent

• Strong expertise in scan insertion, ATPG pattern generation (stuck-at, transition, IDDQ), and fault simulation

• Experience with compression architectures (EDT, DFTMAX) and advanced DFT techniques

• Working knowledge of MBIST architectures and embedded memory test strategies

• Familiarity with JTAG/IEEE 1149.1, IEEE 1500, and IEEE 1687 (iJTAG) standards

• Proficiency in scripting (Tcl, Python, Perl) for DFT flow automation and analysis

• Experience collaborating with physical design and STA teams for scan chain closure

• Strong understanding of digital design fundamentals and RTL design practices

• Passion for mentoring engineers and scaling technical excellence across a team

BONUS POINTS:

• Experience with IEEE P1838 (3D-IC test standards) or die-to-die interface test

• Exposure to at-speed test methodologies, on-chip clock control for at-speed test, and diagnosis flows for yield improvement

• Experience with system-level test and in-system test (IST) approaches

• Familiarity with ATE platforms (Advantest, Teradyne) and test program development

• Expertise in using programming languages and AI tools for test flow automation

• Background in satellite communication, 5G NR, or IoT SoC designs

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.