GreenWave Radios

Ultra low power RF signal processing

Senior Engineer Design Verification

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaIn-person

About the Job

Requirements

A bachelor's and/or master's degree in engineering, or equivalent, in EC, EE, or CS.
At least 5 years of experience verifying DSP block designs, including FFT, FIR, IIR, AGC, interpolation/decimation filters, and up/down converters, using reference models.
Hands-on experience integrating MATLAB or Python models into a UVM environment and creating agents and scoreboard components for DSP blocks.
Knowledge of wireless communication theory, including SNR, IQ constellations, FFT, OFDM, and MIMO.
Experience using Cadence vManager for design verification metrics extraction and regression.
Understanding of the complete verification lifecycle, from test planning and testbench development through coverage closure.
Expertise developing testbench environments and verification components such as monitors, scoreboards, drivers, and agents from scratch.
Proficiency in SystemVerilog, Verilog, UVM, C, Python, Perl, and Tcl/Shell scripting.
Experience developing IP-, subsystem-, or chip-level SystemVerilog and UVM-based verification.
Experience with Git, Jira, and Microsoft Office suites.

Responsibilities

Verify hardware wireless DSP blocks within the design verification team using internally developed MATLAB/Python reference models.
Develop UVM testbench environments and execute verification cases to verify RTL designs with bit-true and cycle-accurate behavior.
Construct SoC-level testbenches by reusing verification components developed at the IP/subsystem level, including testbench architecture for random and directed testing, stimulus generation, and integration of custom and off-the-shelf VIP/UVCs.
Develop and execute verification plans based on design specifications in collaboration with architects and designers.
Construct hardware/software co-verification environments, including testbenches, use cases, APIs, and sequences; execute and debug use cases.
Debug test cases and report verification results to achieve code and functional coverage metrics, using constrained-random verification, functional coverage, code coverage, and assertions.
Assist with emulation, FPGA, and prototyping efforts.
Implement and maintain automated verification flows using languages such as Python and Perl and shell scripts.

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.

Job Description

InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!

Key Responsibilities:

You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model.
Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.
Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.
Develop and execute verification plans based on design specifications and collaboration with architects and designers.
Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases.
Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.
Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
Assist in emulation, FPGA, prototyping efforts.
Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Job Requirements:

Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
5 or more years of experience in DSP blocks(FFT, FIR, IIR, AGC, Interpolation/Decimation Filters, Up/Down Converter) design verification using reference models.
Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks.
Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO)
Experiences in Cadence vManager for DV metrics extraction and regression
Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch.
Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based
Experiences in GIT, JIRA, MS office suites

Benefits:

Competitive salary and stock options.
Learning and development opportunities.
Employer paid health Insurance.
Earned, Casual, Sick & parental leaves.

About the Company

GreenWave Radios

Ultra low power RF signal processing

GreenWave Radios designs energy-efficient RF systems around a specialized hardware architecture called a non-linear Radio Processing Unit (nRPU). Its radios run software-defined protocol personalities that can implement many RF standards on a single hardware platform. The core idea is to execute diverse radio functions in software on the nRPU, achieving much lower power consumption than typical radios while preserving flexibility. This approach lets GreenWave Radios support multiple radio standards and features on one hardware base, enabling easier updates and customization without swapping hardware. The company’s goal is to provide ultra-low-power, flexible radios that can support a wide range of protocols efficiently, addressing the demand for long-lasting, adaptable wireless devices.

Company size: 51-200
Company stage: Not listed
Total funding: Not listed
Headquarters: San Diego, CA
Founded: 2013

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