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AMD

Designs chips for computers and AI systems

Performance and Scalability Engineer - Advanced AI Workloads

Applied Machine LearningPosted on Nov 3
Full-timeSan Jose, CA, USANo salary listed

About the Job

Requirements

  • Software development experience in GPU computing, AI systems, or high-performance computing.
  • Deep hands-on experience with AI serving frameworks such as vLLM, SGLang, TensorRT-LLM, or similar, including their internals.
  • Strong background in end-to-end workload profiling and bottleneck diagnosis, tracing from a user request to a GPU kernel and back.
  • Understanding of GPU kernel performance characteristics, including occupancy, register and LDS pressure, memory coalescing, cache utilization, wavefront scheduling, and instruction-level bottlenecks.
  • Ability to read and reason about kernel-level profiling data and translate it into concrete optimization actions.
  • Understanding of model architectures, including transformers, mixture of experts, and diffusion; inference paradigms, including speculative decoding, prefill-decode disaggregation, and continuous batching; and how they map to hardware.
  • Experience with custom kernel development or integration using HIP, CUDA, Triton, CK, or similar.
  • Understanding of multi-GPU and multi-node distributed systems, including scale-up and scale-out topologies, RCCL/NCCL, RDMA, and communication-compute overlap.
  • System and rack-level design awareness, including performance tradeoffs across the full deployment stack.
  • Strong proficiency in Python and C++.
  • Customer-facing technical leadership experience, including engaging with customers, presenting findings, and driving decisions.
  • Fluency in AI-assisted development, with daily use of AI agents and tools and a mindset toward defining new AI-powered workflows.
  • Strong Linux systems knowledge.
  • Excellent written and verbal English communication skills.

Responsibilities

  • Drive end-to-end performance optimization across the stack on leading models and customer-relevant serving configurations, closing competitive gaps through kernel and systems-level optimizations.
  • Profile, diagnose, and resolve cross-stack performance bottlenecks, from GPU kernels and operator dispatch to framework-level scheduling and multi-node communication.
  • Diagnose kernel-level performance issues using profiling tools, identify occupancy limitations, L2 cache thrashing, register pressure, and memory coalescing issues, and translate findings into actionable optimizations.
  • Lead customer-facing technical engagements by presenting findings, recommending optimizations, and delivering measurable performance improvements.
  • Integrate and optimize custom kernels (Triton, Gluon, CK, PyDSL, ASM, and AITER) within serving frameworks, understanding dispatch paths, shape extraction, and backend selection.
  • Optimize multi-node distributed inference, including communication-compute overlap, parallelism strategies, and scale-out performance.
  • Develop and refine shared performance optimization methodology that raises the bar across the broader team.
  • Leverage AI agents to accelerate daily work and define best practices for AI-assisted performance engineering.
  • Upstream optimizations into open-source frameworks such as vLLM, SGLang, and PyTorch.

Desired Qualifications

  • A Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, or Electrical Engineering, or an equivalent credential; an advanced degree is preferred, though exceptional industry experience is valued equally.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1969

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