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MatX

Designs high-throughput AI hardware chips

Senior SoC Power Analysis & Optimization Engineer

Silicon & ASIC DesignUpdated on Nov 14
Full-timeMountain View, CA, USA

About the Job

Requirements

  • A BS or MS in Electrical Engineering, Computer Engineering, or a related field is required.
  • At least 8 years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design is required.
  • Strong understanding of computer architecture and SoC design is required.
  • Experience with ASIC low-power design techniques is required.
  • Experience performing RTL and gate-level power analysis is required.
  • Experience with Python, Perl, or similar scripting languages is required.

Responsibilities

  • Develop and maintain power estimation methodologies for AI accelerator SoCs.
  • Build and calibrate energy models for early architectural exploration, design trade-off analysis, and power target definition.
  • Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.
  • Analyze AI workloads and application use cases to identify opportunities for dynamic and static power reduction.
  • Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other SoC subsystems.
  • Collaborate with architects and RTL designers to implement power-efficient microarchitecture and RTL improvements.
  • Work with physical design teams to evaluate implementation-related power trade-offs.
  • Define representative workloads and sign-off scenarios to improve power analysis coverage.
  • Develop automation, scripts, dashboards, and heuristics to accelerate power analysis and root-cause investigation.
  • Present power analysis results, optimization proposals, and design recommendations to cross-functional teams.

Desired Qualifications

  • RTL development experience using Verilog/SystemVerilog.
  • Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design.
  • Experience with synthesis, static timing analysis, place-and-route, and implementation flows.
  • Experience using power analysis tools such as Joules, PowerArtist, and PrimeTime PX (PTPX/PPRTL), or equivalent tools.
  • Experience developing power models, budgeting methodologies, and projection flows.
  • Experience analyzing large power datasets using scripting and data analytics.
  • Experience with power management techniques, including clock gating, power gating, and dynamic power management.
  • Experience correlating pre-silicon power estimates with silicon measurements.
  • Experience with AI workload characterization and power-performance analysis.

About the Company

MatX

Designs high-throughput AI hardware chips

MatX builds high-throughput AI accelerators for large language models. Its main product is a dedicated chip where every transistor is optimized for running large neural networks, aiming to deliver strong performance for training and inference of LLMs. The company also develops the surrounding software stack, including compilers, to make the hardware easy to program for ML engineers (e.g., through JAX-based workflows). Unlike general-purpose processors, MatX focuses on specialization and full-stack optimization from silicon to software. Its goal is to enable organizations with substantial AI workloads to scale efficiently by providing powerful, purpose-built hardware and the compatible software tools they need to deploy and optimize large models.

Company size
51-200
Company stage
Series B
Total funding
$604.9M
Headquarters
Mountain View, CA
Founded
2022

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