Program Manager - Chip Design

Key Responsibilities

Program Planning & Execution

• Own end‑to‑end program plans for chip design programs from concept → tape‑out → silicon bring‑up.
• Develop and maintain coordinated schedules, achievements, and critical paths across:
  • Architecture
  • RTL & DV
  • Physical Design
  • CAD / Methodology
  • DFT, AMS, Packaging, and Silicon Validation
• Drive program reviews, achievement readiness, and stage‑gate decisions.

Multi-Functional Leadership

• Act as the primary interface between Design, Verification, Layout, CAD, Technology, Product Engineering, Manufacturing, and Business teams.
• Drive alignment across global teams (India, US, Japan, etc.).
• Resolve cross‑team dependencies, priority conflicts, and execution bottlenecks.

Risk, Issue & Transition Coordination

• Proactively identify schedule, technical, resource, and dependency risks.
• Drive mitigation and recovery plans for execution gaps.
• Own change control for scope, schedule, and resource adjustments.

Execution Metrics & Reporting

• Define and track program critical metrics:
  • Schedule health
  • Resource loading
  • Design & verification readiness
  • Tape‑out quality indicators
• Provide clear, concise executive updates with data‑driven insights.
• Ensure clarity through dashboards and weekly program reports.

Quality & Process Excellence

• Ensure compliance with product lifecycle management (PLM), design sign‑off criteria, and quality gates.
• Drive post‑mortems / retrospectives and institutionalize findings.
• Partner with CAD and methodology teams to improve design productivity and predictability (automation, AI, tooling).

Partner & Leadership Communication

• Serve as the single point of accountability for program status.
• Get along with senior leadership, including trade‑offs, risks, and decision asks.
• Influence without authority and drive execution through teamwork.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical / Electronics / Computer Engineering (or equivalent).
• 8–15+ years of experience in semiconductor / chip design programs.
• Strong understanding of chip design flows, including:
  • Architecture & RTL
  • Design Verification
  • Physical Design / PnR
  • Tape‑out and silicon lifecycle
• Proven experience managing large, multi-functional, multi-site programs.
• Strong skills in schedule management, risk management, and executive communication.

Preferred Qualifications

• Hands‑on background in RTL, DV, PD, or CAD (prior technical role strongly preferred).
• Experience with memory (DRAM / LPDDR / HBM) or complex SoC programs.
• Exposure to build and verification flows guided by advanced technology.
• Experience driving process improvements and automation in design execution.

Key Success Attributes

• Strong ownership approach and execution rigor.
• Ability to operate in high ambiguity, fast‑paced environments.
• Excellent customer management and influencing skills.
• Data‑driven, structured problem solver with attention to detail.
• Collaborative leader with a global approach.

Impact of the Role

• Enable predictable, high‑quality tape‑outs.
• Improve design cycle time and execution efficiency.
• Serve as a critical pillar connecting engineering execution with business outcomes.