Design Verification Engineer Intern

Design Verification Engineer – Intern

Role overview

Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional verification of high-performance connectivity and networking ASICs.

You will work with experienced design and verification engineers to understand design specifications, develop and execute verification tests, debug simulation failures, and help assess the functionality and reliability of complex digital designs. You will collaborate with RTL design, architecture, and other engineering teams throughout the ASIC development process.

Key responsibilities

Functional verification and test development

• Assist in developing and executing simulation-based test plans for digital ASIC blocks and subsystems.

• Develop and maintain test cases using SystemVerilog and other verification languages under the guidance of experienced engineers.

• Help identify functional scenarios, corner cases, and potential design issues from design specifications.

• Run simulations and analyze results to verify that RTL behavior meets design requirements.

• Contribute to test quality, verification efficiency, and functional coverage improvements.

Simulation debugging and design quality

• Debug simulation failures using waveforms, simulation logs, and debugging tools.

• Work with RTL design engineers to investigate functional issues and help identify root causes.

• Assist with regression testing and track verification results.

• Learn and apply verification best practices, including assertions, functional coverage, and systematic debugging.

• Help maintain verification environments and test documentation.

Verification methodology and automation

• Gain exposure to SystemVerilog-based verification environments and object-oriented programming concepts.

• Learn Universal Verification Methodology (UVM) and contribute to existing testbenches as appropriate.

• Assist with reusable verification components, test sequences, and checkers.

• Use Python, Tcl, Shell, or similar scripting languages to automate repetitive verification tasks.

• Participate in code reviews and contribute to verification-code quality and maintainability.

Cross-functional collaboration

• Collaborate with RTL design, architecture, and verification engineers to understand design functionality and verification requirements.

• Participate in design reviews, verification planning, and technical discussions.

• Document test scenarios, debugging results, and verification progress.

• Gain exposure to ASIC development milestones, including block integration, regression signoff, tapeout, and post-silicon validation.

Basic qualifications

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Fundamental understanding of digital logic design, including combinational and sequential logic, flip-flops, finite state machines, and basic datapaths.

• Basic programming knowledge in at least one language such as C, C++, Python, or SystemVerilog.

• Basic understanding of hardware design concepts, including clocks, resets, registers, and state machines.

• Familiarity with digital simulation or hardware design through coursework, academic projects, research, or internships.

• Strong analytical, problem-solving, and debugging skills.

• Willingness to learn new verification tools, methodologies, and technologies.

• Good communication skills and the ability to work effectively in a collaborative team environment.

• Ability and willingness to work onsite in San Jose, California.

• No prior industry experience is required; relevant coursework, academic projects, research, and internships will be considered.

Preferred qualifications

• Experience with Verilog or SystemVerilog through coursework, academic projects, or internships.

• Exposure to RTL simulation tools and waveform debugging.

• Familiarity with digital-design verification concepts, testbench development, or functional coverage.

• Basic knowledge of object-oriented programming or SystemVerilog assertions.

• Exposure to UVM or other constrained-random verification methodologies.

• Experience with Python, Tcl, Perl, Shell, or other scripting languages for automation.

• Familiarity with ASIC or FPGA development flows.

• Exposure to high-speed interfaces or protocols such as PCI Express, Ethernet, AMBA, CXL, NVMe, or other networking and interconnect technologies.

• Interest in high-performance ASICs, networking, data-center infrastructure, AI accelerators, or cloud computing.

• Demonstrated ability to learn complex technical concepts and apply them to practical engineering problems.

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.