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Synopsys

EDA software for chip design

Applications Engineering - Staff Engineer-19323

Hardware Validation & TestingUpdated on Nov 11
Full-timeNo salary listed

About the Job

Requirements

  • A BSEE or MS and at least 10 years of related experience.
  • Expertise in emulation and/or prototyping flows, systems, and methodologies.
  • Strong proficiency in Verilog, SystemVerilog, VHDL, and C/C++.
  • Understanding of verification concepts and experience with functional simulators.
  • Experience with scripting languages such as Python and Tcl.
  • Knowledge of simulation flows, assertion, DPI, and transactors.
  • Complex problem-solving and debugging skills.
  • Strong communication skills and ability to interact with customers and peers.

Responsibilities

  • Collaborate closely with R&D and customers on hardware-assisted verification products.
  • Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.
  • Define test strategies and methodologies to improve ease of use, quality of results, and interoperability with other Synopsys tools.
  • Develop expertise in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.
  • Demonstrate the emulation and verification environment through interaction with customers, R&D, Marketing, and Sales teams.
  • Follow recognized best practices and Synopsys policies and become proficient in processes involved in the Product Release Cycle.
  • Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.
  • Enhance emulation and prototyping solutions by driving technology development and customer deployment.
  • Improve the ease of use, quality of results, and interoperability of Synopsys tools.
  • Provide expert consultation to solve complex problems and increase customer satisfaction and product adoption.
  • Ensure successful execution of projects from start to completion and contribute to timely delivery of high-quality products.
  • Support advancement of designs in verticals including HPC, AI, storage, networking, and automotive.
  • Facilitate adoption of the emulation and verification environment through collaboration with multiple teams.

Desired Qualifications

  • Knowledge of synthesis and timing analysis concepts.
  • Familiarity with Synopsys tools including ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality.
  • Experience with Xilinx and Altera architectures and toolchains.
  • Knowledge of protocols including PCIe, USB, Ethernet, DRAMs, HBM, and NAND Flash.
  • Knowledge of computing systems, including CPU architecture and operating systems.
  • Understanding of software/hardware debugging methodologies and experience with standard software/hardware debugging tools.
  • Knowledge of DFT solutions.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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