Director of Analog and Mixed-Signal IC Design
Neurophos
Director of Analog and Mixed-Signal IC Design
Neurophos
Optical metasurface AI accelerators
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Location: Austin, TX. Full-time onsite position.
Reports To: VP of VLSI
FLSA Status: Exempt
Neurophos is seeking a Director of Analog and Mixed-Signal IC Design to build and lead the team responsible for the electronic circuits that drive, sense, and connect our optical processing unit. Our OPU depends on dense, energy-efficient electronics operating in close partnership with photonics: high-speed data converters and drivers that move information into and out of the optical domain, low-power analog front ends that read out the photonic signals, clocking and power management that keep the system stable, and high-bandwidth links that connect it to the rest of the data center.
In this role, you will build and run the analog, mixed-signal, and mmWave design organization and own its silicon from architecture through volume production. You will set technical direction, lead and grow a team of senior designers, and own delivery of silicon that meets performance, power, schedule, and yield targets. We are looking for a highly technical leader who has taken multiple products from concept to high-volume manufacturing and knows what it takes to design for first-pass success and production robustness.
Build, lead, and mentor a high-performing team of analog, mixed-signal, RF/mmWave, and layout engineers; recruit top talent and foster a culture of technical rigor, ownership, and collaboration.
Define the architecture and specifications for analog and mixed-signal IP, including high-speed ADCs and DACs, modulator drivers, transimpedance amplifiers and analog front ends, PLLs and clock generation/distribution, SerDes and high-speed I/O, voltage references, and on-chip regulators.
Own silicon through the full lifecycle: specification, schematic and layout, verification, tape-out, silicon bring-up, characterization, qualification, and production release.
Represent analog within the company. Negotiate specifications, schedules, and budgets the team can meet. Keep the team informed of company priorities and decisions, and report status, risks, and mitigation plans to the VP of VLSI.
Guide the design of low-power precision analog blocks and high-speed mixed-signal circuits, driving aggressive energy-per-operation targets across the OPU system.
Collaborate with the photonics team and oversee the development of millimeter-wave circuits and interfaces, including transceivers, LNAs, PAs, mixers, VCOs, and high-frequency passives, with a focus on EM modeling and package co-design.
Maintain disciplined design data management. Establish and enforce robust design methodologies: PVT and Monte Carlo analysis, reliability (EM/IR, aging, ESD, latch-up), mismatch and noise budgeting, and rigorous design reviews at every milestone.
Evaluate and adopt new tools, including AI-assisted design and verification.
Drive design-for-manufacturability and design-for-test, working with test engineering to define strategy, trim and calibration schemes, and production test coverage.
Lead silicon debug and root-cause analysis, and drive yield improvement and corner-lot correlation with foundry, OSAT, and product engineering partners.
Partner closely with the photonics, digital, packaging, systems, and firmware teams to co-optimize the electro-optical interface and ensure system-level integration.
15+ years of experience in analog, mixed-signal, and/or RF IC design, including 5+ years leading design teams at the manager or director level.
Proven track record of bringing analog/mixed-signal products from concept through tape-out and validation into high-volume production, including qualification, yield ramp, and production test.
Deep, hands-on expertise in low-power, high-precision analog and high-speed mixed-signal design, including data converters, PLLs, high-speed transceivers, and amplifiers.
Demonstrated experience with millimeter-wave or high-frequency RF circuit design and the associated EM simulation, modeling, and measurement techniques.
Strong working knowledge of advanced CMOS, FinFET, and/or SiGe BiCMOS process technologies and their implications for analog performance and reliability.
Proficiency with industry-standard design and verification flows, including Cadence Virtuoso and Spectre and EM tools such as EMX.
Experience working with foundries and OSATs, and a solid understanding of DFT, ATE test development, trimming and calibration, and failure analysis.
Structured, organized approach to running a team and a design flow. Adaptable as tools, priorities, and the organization change.
PhD in Electrical Engineering, Computer Engineering, Physics, or related fields.
Experience designing electronics for integrated photonics or optical interconnects, such as modulator drivers, TIAs, laser drivers, or co-packaged optics.
Background in electronic-photonic co-design, including heterogeneous integration or 3D stacking of electronic and photonic dies.
Experience with high-speed (e.g., 112G/224G PAM4 SerDes) wireline standards or mmWave wireless/radar products.
Experience with ultra-low-power circuit techniques, including subthreshold design, dynamic power management, and energy-efficient data conversion.
Familiarity with advanced packaging, signal and power integrity, and chip-package-board co-simulation.
Experience building a team and supporting infrastructure in a startup setting.
A record of patents, publications, or recognized contributions.
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Join a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Neurophos designs AI accelerator chips built with optical metasurfaces and silicon photonics to deliver high-density, energy-efficient AI computation for data centers. Its processors are designed to shrink optical components by about 8000x, increasing compute power per dollar spent and reducing both capital and operating expenditures. The product works by using optical processing techniques that handle AI inference workloads more efficiently than traditional GPUs or electronic AI accelerators, enabling faster throughput with lower power use. Neurophos differentiates itself by combining optical metasurfaces with silicon photonics to achieve higher density and energy efficiency, targeting data centers and enterprises that need scalable, cost-sensitive AI inference. The company aims to reshape the AI landscape by offering faster, denser, and more energy-efficient AI computation while lowering the total cost of ownership for data centers.
Explore more opportunities at Neurophos