AMD

Designs chips for computers and AI systems

Technical Fellow - High-Speed Interconnect & Optics

Hardware Systems IntegrationConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USANo salary listedIn-person

About the Job

Requirements

Deep expertise in high-speed signal integrity and power integrity, including power delivery networks, for data rates of 112G, 224G, and beyond.
Experience with pluggable optics, including QSFP and OSFP, co-packaged optics, co-packaged copper, and on-board optics.
Experience in optical packaging and system integration, including silicon photonics, laser coupling strategies, and thermal and power management at scale.
Hands-on experience with system bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems.
Strong understanding of SerDes architecture, equalization, forward error correction, and system-level channel modeling.
Ability to lead across organizational boundaries and influence vendors, partners, customers, and standards bodies.
Track record of sustained technical leadership and architectural impact across multiple product generations.
Master’s degree in Computer Science, Electrical Engineering, Photonics, or a related technical field.

Responsibilities

Define and advance system-level interconnect architecture for next-generation AI, HPC, and data center platforms.
Drive innovation across electrical and optical interconnect technologies spanning ASICs, advanced packaging, boards, optics, and full-system integration, while shaping industry direction and AMD’s long-term technology roadmap.
Define architecture and long-term strategy for electrical and optical interconnects, including pluggable optics, co-packaged optics, co-packaged copper, and on-board optics, enabling scalable AI scale-up and scale-out system architectures.
Provide technical authority and leadership in high-speed signal integrity and power delivery network design across ASICs, packages, boards, connectors, and optical interfaces; ensure end-to-end performance at 112G, 224G, and beyond under real-world system operating conditions.
Drive end-to-end optical system integration, including optics module architecture, silicon photonics, internal and external laser integration, advanced packaging solutions, and thermal and power optimization for high-density systems.
Influence SerDes architecture, specifications, modeling assumptions, and tuning strategies to align ASIC design with channel behavior, optical characteristics, packaging constraints, and system-level requirements.
Serve as a hands-on technical authority during lab bring-up, characterization, and system debug; resolve complex issues spanning signal and power integrity, optics, firmware, packaging, and system-level interactions across development and deployment phases.
Represent AMD in industry standards bodies and consortia, including OIF, IEEE, and PCI-SIG; influence next-generation specifications, drive ecosystem alignment, and align AMD’s interconnect roadmap with industry trends.
Mentor senior engineers, architects, and emerging technical leaders; establish best practices, architectural frameworks, and design guidelines across teams and business units.
Advise senior leadership on technical matters and drive technical trade-offs, vendor and partner strategy, and product go/no-go decisions affecting product direction, risk, cost, and time-to-market.

Desired Qualifications

Recognized industry or academic thought leadership; publications and patents are a strong plus.
A PhD.

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

The Technical Fellow for High-Speed Interconnect and Optics is a senior technical leader responsible for defining and advancing NTSG’s system-level interconnect architecture for next-generation AI, HPC, and data center platforms. This role drives innovation across electrical and optical interconnect technologies—spanning ASICs, advanced packaging, boards, optics, and full-system integration—while shaping industry direction and contributing to AMD’s long-term technology roadmap

THE PERSON:

Defining next-generation interconnect architecture in thisLead role and long-term strategy for next-generation electrical and optical interconnects, including pluggable optics, co-packaged optics (CPO), co-packaged copper (CPC), and onboard optics (OBO), enabling scalable AI scale-up and scale-out system architectures.

KEY RESPONSIBILITIES:

Drive System-Level SI/PI Excellence

Provide technical authority and leadership in high-speed signal integrity (SI) and power delivery network (PDN) design across ASICs, packages, boards, connectors, and optical interfaces. Ensure robust, end-to-end performance at 112G, 224G, and beyond under real-world system operating conditions.

Lead Optical System Integration and Packaging Innovation

Drive end-to-end optical system integration, including optics module architecture, silicon photonics, laser integration (internal and external), advanced packaging solutions, and thermal and power optimization for high-density systems.

Guide SerDes and ASIC Co-Optimization

Influence SerDes architecture, specifications, modeling assumptions, and tuning strategies to ensure alignment between ASIC design and real-world channel behavior, optical characteristics, packaging constraints, and system-level requirements.

Hands-On Technical Leadership and Debug

Serve as a hands-on technical authority during lab bring-up, characterization, and system debug. Resolve complex, cross-layer issues spanning SI/PI, optics, firmware, packaging, and system-level interactions across development and deployment phases.

Shape Industry Direction and Ecosystem Alignment

Represent AMD as a technical leader in industry standards bodies and consortia (e.g., OIF, IEEE, PCI-SIG). Influence next-generation specifications, drive ecosystem alignment, and ensure AMD’s interconnect roadmap leads and aligns with industry trends.

Mentor and Multiply Technical Impact

Mentor senior engineers, architects, and emerging technical leaders. Establish best practices, architectural frameworks, and design guidelines to elevate technical excellence across teams and business units.

Influence Business and Product Strategy

Act as a trusted technical advisor to senior leadership. Drive critical technical trade-offs, vendor and partner strategy, and product go/no-go decisions that materially impact product direction, risk, cost, and time-to-market.

PREFERRED QUALIFICATIONS:

Deep expertise in high-speed signal integrity and power integrity (SI/PI, PDN) for advanced data rates (112G, 224G, and beyond).
Strong experience across optical interconnect technologies, including:

Pluggable optics (QSFP, OSFP)
Co-Packaged Optics (CPO)
Co-Packaged Copper (CPC)
On-Board Optics (OBO)

Proven experience in optical packaging and system integration, including silicon photonics, laser coupling strategies, and thermal and power management at scale.
Hands-on experience with system bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems.
Strong understanding of SerDes architecture, equalization, FEC, and system-level channel modeling.
Demonstrated ability to lead across organizational boundaries and influence vendors, partners, customers, and standards bodies.
Track record of sustained technical leadership and architectural impact across multiple product generations.
Recognized industry or academic thought leader;publications and patents astrong plus

ACADEMIC CREDENTIALS:

Master’s in Computer Science, Electrical Engineering, Photonics, or a related technical field, PhD preferred

Location:

Santa Clara, CA

This role is not eligible for visa sponsorship.

#LI-RF1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size: 10,001+
Company stage: IPO
Headquarters: Santa Clara, CA
Founded: 1969

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