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Micron Technology

Makes memory and storage chips for AI and PCs

Principal System-on-Chip DFT Engineer - HBM

Hardware Validation & TestingPosted on Nov 12
Full-timeIn-person

About the Job

Requirements

  • Strong hands-on experience with SoC DFT architecture and implementation.
  • Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
  • Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, static timing analysis, and physical design.
  • Experience working with large, complex SoCs involving multiple IPs and subsystems.
  • Proficiency with industry-standard electronic design automation tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
  • Strong RTL debugging and design analysis skills.
  • Familiarity with scripting languages such as Python, Tcl, or Perl for flow automation.
  • Familiarity with memory systems (DRAM/HBM) and JEDEC specifications is a strong plus.
  • Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.
  • At least 10 years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.

Responsibilities

  • Own SoC-level DFT implementation, including scan, MBIST, LBIST as applicable, boundary scan (JTAG), and test access architectures for HBM base-die designs.
  • Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design constraints.
  • Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
  • Own DFT flow execution and signoff, including lint, clock-domain crossing checks, DFT rule checks, ATPG readiness, and coverage closure.
  • Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and DRC/LVS signoff.
  • Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
  • Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
  • Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
  • Maintain technical expertise and mentor junior engineers as appropriate.
  • Drive innovation into future HBM generations, focusing on quality, scalability, and manufacturability.
  • Develop generative-AI-driven tools, workflows, and methodologies leveraging agentic AI.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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