STA / Synthesis Engineer – Staff / Sr. Staff / Principal

Role Overview

As a Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI, you will own RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon. You will be responsible for driving implementation quality, timing convergence, power optimization, and sign-off readiness
for complex compute, CPU, VPU, and low-power cores targeting advanced process technologies. You will work closely with RTL, architecture, DFT, physical design, CAD, verification, and product engineering teams to achieve aggressive Performance, Power, Area, and Cost targets. This is a highly visible technical role where you will influence
synthesis strategy, timing closure methodology, constraint quality, ECO flows, and implementation best practices for complex ASIC/SoC designs.

Responsibilities

● Drive RTL-to-gate synthesis for complex compute, CPU, VPU, AI accelerator, and low-power cores using industry-standard synthesis tools.

● Own synthesis setup, constraints, optimization, quality checks, and netlist delivery for block-level and subsystem-level designs.

● Lead static timing analysis and timing closure activities across multiple modes, corners, voltage domains, and clock domains.

● Optimize designs for timing, power, area, and cost while meeting aggressive design targets and schedule requirements.

● Develop, validate, and maintain high-quality timing constraints, including full-chip, block-level, generated clock, false path, multicycle path, and interface constraints.

● Drive multi-mode multi-corner timing analysis, constraint management, timing debug, and convergence across all sign-off scenarios.

● Work closely with RTL, DFT, physical design, and verification teams to resolve timing, constraints, clocking, reset, DFT, and low-power implementation issues.

● Own timing sign-off readiness and ensure compliance with timing, power, signal integrity, and implementation quality requirements.

● Drive hierarchical timing closure across blocks, subsystems, and full-chip interfaces.

● Implement and optimize low-power design strategies including clock gating, multi-voltage domains, power-aware synthesis, and UPF/CPF-based power intent flows.

● Execute timing ECO flows for setup, hold, transition, capacitance, noise, and late-stage design closure.

● Support physical-aware synthesis, placement-aware optimization, and collaboration with physical design teams to improve timing and PPA correlation.

● Define and improve synthesis, STA, constraints, ECO, and timing closure methodologies for high-quality and efficient implementation.

● Evaluate and deploy EDA tools, flows, and automation to improve runtime, productivity, quality of results, and turnaround time.

● Develop scripts using Tcl, Perl, Python, or other languages to automate synthesis, STA, reporting, debug, and flow validation.

● Collaborate with geographically distributed teams and provide technical leadership in implementation, timing closure, and sign-off quality.

Required Qualifications

● 5–15 years of hands-on experience in ASIC/SoC implementation, synthesis, STA, and timing closure.

● Strong experience with RTL-to-gate synthesis and timing closure for complex digital designs.

● Proven experience working on compute, CPU, VPU, AI accelerator, SoC, or high-performance digital IP designs.

● Strong expertise in industry-standard synthesis and STA tools from Synopsys and Cadence.

● Excellent understanding of multi-mode multi-corner timing analysis, constraint development, timing debug, and sign-off methodology.

● Hands-on experience with hierarchical timing closure, block-level timing closure, subsystem-level timing closure, and full-chip timing convergence.

● Experience with advanced process technologies, including 2nm, 3nm, or other leading-edge nodes.

● Strong understanding of low-power design strategies, multi-clock domain designs, clock gating, multi-voltage domains, and power-aware implementation.

● Experience with UPF/CPF-based power intent, power-aware synthesis, isolation, level shifters, retention, and low-power timing closure.

● Extensive experience with ECO flows for timing fixes, functional changes, late-stage design updates, and sign-off closure.

● Strong scripting skills in Tcl, Perl, or Python for automation of synthesis, STA, reporting, and debug flows.

● Strong analytical, debugging, problem-solving, communication, teamwork, and execution skills.

● Ability to work effectively across highly experienced global teams in a fast-paced engineering environment.

Preferred Qualifications

● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, VLSI, or a related discipline.

● Experience with timing sign-off for chiplet-based designs, multi-die architectures, or advanced package-based silicon platforms.

● Good understanding of physical design implementation, floorplanning, placement-aware synthesis, clock tree synthesis, routing, and physical timing closure.

● Experience with signal integrity, crosstalk, noise analysis, timing derates, OCV/AOCV/POCV, and advanced timing variation methodologies.

● Familiarity with DFT timing, scan modes, OCC, test constraints, MBIST/LBIST timing, and test-mode closure.

● Experience developing synthesis and timing closure methodologies for cost-sensitive and high-performance designs.

● Experience evaluating EDA tools, improving implementation recipes, and driving quality-of-results improvements.

● Ability to propose innovative and leading-edge solutions for timing closure, synthesis optimization, and design convergence.

● Track record of driving complex technical issues to closure with attention to detail and strong ownership.

● Experience with 2nm, 3nm, or other leading-edge process technologies.

● Experience with chiplet-based designs, advanced packaging, inter-die interfaces, or multi-die timing closure.

● Knowledge of AI/HPC architectures, processor pipelines, vector processing units, NoC fabrics, or memory subsystem timing challenges.

● Experience with physical-aware synthesis, congestion-aware optimization, placement-aware timing analysis, and PPA correlation.

● Familiarity with sign-off quality checks including timing, power, signal integrity, noise, transition, capacitance, and clock quality.

● Exposure to silicon bring-up, timing correlation, production support, and post-silicon debug.

● Experience driving methodology improvements, EDA automation, and flow standardization across teams.

● Strong technical leadership, mentoring, communication, and cross-functional collaboration skills.

● Can-do attitude, openness to new environments, people, and cultures.

● Passion for solving complex timing and implementation challenges while delivering high-quality silicon under aggressive schedules.

● Background in RTL-to-gate synthesis and implementation; Static Timing Analysis and timing sign-off; multi-mode multi-corner timing closure; constraint development and validation; compute, CPU, VPU, AI accelerator, and
high-performance digital IP implementation; low-power synthesis and power-aware timing closure; UPF/CPF-based power intent implementation; hierarchical timing closure and full-chip timing convergence; timing ECO,
functional ECO, and late-stage design closure; EDA flow automation and synthesis/STA methodology development; or cross-functional silicon development with RTL, DFT, physical design, CAD, verification, and product engineering teams.