Principal Engineer - Analog and Mixed-Signal Design-Technology Co-Optimization

Job Details:

Job Description: 

The Group:

Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal, RF, and high-speed I/O IP that defines what Intel Foundry's leading-edge process technologies can deliver. The AMS Design-Technology Co-Optimization (DTCO) team sits at the intersection of process technology, design rules, PDK, EDA tools, and circuit design, making sure each new node delivers competitive analog, mixed-signal, and custom-design density, performance, and productivity.

The Role:

We are seeking a senior technical leader in DTCO to define and drive co-optimization of Intel Foundry's next-generation process technologies for analog, mixed-signal, and custom design. You will identify where technology definition limits design outcomes (density, drive, matching, high-voltage support, layout productivity), quantify the impact, and drive resolution across process, design-rule, PDK, EDA, and design teams. This is a senior individual-contributor role with technical leadership across multiple organizations and external EDA partners.

Responsibilities:

• Lead AMS DTCO for future Intel Foundry nodes: evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements.
• Run a closed-loop DTCO process: sense issues from designers, partners, and test chips; prioritize by PPA and productivity impact; drive rule, PDK, or flow changes; and validate the result on silicon and in design.
• Quantify technology impact on circuits through layout studies, parasitic-aware benchmarking, and area and performance scaling analysis of representative AMS building blocks.
• Define and drive design-rule and PDK requirements with process, design-rule, OPC, and quality and reliability teams, including high-voltage device support, density and fill rules, metal width and spacing options, and layout-dependent effects.
• Partner with EDA vendors on node enablement for custom and AMS flows: custom layout, analog placement and routing, physical verification, fill, and extraction; translate tool and flow feedback into technology decisions.
• Represent Intel Foundry in technical engagements with EDA partners and foundry customers, and present DTCO findings and recommendations to technology and business leadership.
• Mentor engineers and set technical direction for the DTCO team.

Required Skills and Experience:

• 5+ years of DTCO experience for analog, mixed-signal, I/O, or custom design on FinFET or more advanced process nodes, at a foundry, an IDM technology-development organization, or an EDA vendor.
• And experience in at least one of the following:
  • Design-rule definition for analog or custom layout, including layout-pattern studies, layout-dependent effects, and test-structure design to evaluate rule impact.
  • Circuit-level technology benchmarking of analog or mixed-signal building blocks: device-model and parasitic evaluation, matching, and area or performance scaling analysis.
  • EDA tool or flow enablement of analog and custom design for a new process node: custom layout, analog placement and routing, physical verification, fill, or extraction.

Preferred Skills and Experience:

• Hands-on analog, mixed-signal, or RF circuit design experience (for example PLLs, data converters, regulators, high-speed I/O, LNAs, PAs, or mmWave front ends), with an understanding of how device and interconnect parameters drive circuit performance.
• Analog and RF device and passive technology: precision resistors, MIM/MOM capacitors, inductors and transformers, varactors, analog and RF device flavors, and RF figures of merit such as fT, fmax, and noise figure.
• Experience across two or more of the areas in the minimum qualifications, or across both foundry and EDA environments.
• High-voltage or extended-voltage device integration on advanced CMOS nodes.
• Analog or custom layout design experience.
• Gate-all-around transistors, backside power delivery, or advanced multi-patterning (SALELE, EUV) technology definition as it affects analog and custom layout.
• Automation of DTCO studies using Python, layout generators, or machine learning.
• Customer-facing technical engagement with foundry customers or EDA partners.
• Publications at IEDM, VLSI Symposium, CICC, ISSCC, or RFIC; patents in DTCO, design rules, design enablement, or AMS/RF circuits.
• Technical leadership across process, design, and EDA organizations, including driving technology-definition decisions at node level.

Qualifications:

• Advanced degree in Electrical Engineering, Computer Engineering, Materials Science, Physics, or a related field
• Industry experience in semiconductor technology development, design enablement, or circuit design
• Master's degree with 15+ years of experience OR Ph.D. with 12+ years of experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.