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Upscale AI

High-performance AI networking hardware and software

Principal Engineer RTL Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

  • Solid background in Digital IC Design, including micro-architecture, RTL design, logic synthesis, timing closure, and low-power design techniques.
  • Familiarity with industry-standard electronic design automation tools, such as Cadence, Synopsys, and Mentor, for simulation, synthesis, and static timing analysis.
  • Knowledge of ASIC design flows and verification methodologies, and ability to collaborate with physical design and validation teams.
  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, or equivalent practical experience.
  • Track record of success with multiple ASIC tape-outs.
  • 10+ years of industry experience in ASIC design.

Responsibilities

  • Perform end-to-end ASIC design activities, including architecture exploration, micro-architecture definition, logic design, and RTL development.

Desired Qualifications

  • Experience with networking ASIC design.
  • Experience in post-silicon ASIC bring-up.

About the Company

Upscale AI

High-performance AI networking hardware and software

Upscale AI builds a full-stack, high-performance AI networking platform to scale up GPU compute. It designs purpose-built silicon chips and a software orchestration layer that connects thousands of GPUs into a single, unified compute engine. The system is optimized for the heavy data movement and bursty traffic of large language model training and inference, enabling fast, scalable AI workloads. Unlike traditional, vendor-driven networking stacks, Upscale AI offers open-standard networking powered by silicon and software, and participates in consortia like UEC and SONiC to ensure interoperability across different hardware environments. Its customers include global hyperscalers, AI-first enterprises, and sovereign cloud providers who need large-scale, interoperable AI clusters without lock-in. The company’s goal is to democratize AI infrastructure by delivering high-performance, open-standard solutions that let organizations build and operate massive AI clusters more efficiently.

Company size
201-500
Company stage
Series A
Total funding
$490M
Headquarters
Santa Clara, CA
Founded
2024

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