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Positron

Memory-first AI inference silicon for LLMs

Architecture & Performance Modeling Engineer – Senior / Principal - AI Inference Silicon

Hardware EngineeringPosted on Nov 14
Full-timeRemote in USA

About the Job

Requirements

  • At least 5 years of experience in computer architecture, microarchitecture, or performance modeling for accelerators, CPUs, or GPUs.
  • Demonstrated experience using models to influence architectural decisions, such as identifying a bottleneck, comparing design alternatives, or recommending a change backed by quantitative analysis.
  • Strong understanding of pipelines, queues, parallel execution, memory hierarchies, data movement, and interconnects.
  • Hands-on experience building analytical, transaction-level, or cycle-level performance models, including first-order estimates that help validate and explain simulation results.
  • Ability to work with incomplete specifications, make assumptions explicit, and balance modeling fidelity with speed of iteration.
  • Strong Rust skills, or expert-level C/C++ skills and willingness to work in Rust day to day, along with proficiency in Python for workload analysis, experiments, and visualization.
  • Ability to read SystemVerilog RTL and relevant verification results, reconcile them with architectural specifications, and calibrate models as implementation details become available.
  • Ability to explain what drives a result, the confidence level in it, and what the architecture team should investigate or change next.

Responsibilities

  • Partner with architects to turn design questions into focused modeling studies with clear assumptions, alternatives, metrics, and recommendations.
  • Perform what-if analysis across compute engines, memory capacity and bandwidth, dataflow, DMA, command processing, on-chip interconnect, and chip-to-chip communication.
  • Compare architectural options, explain performance sensitivities, and recommend changes within system, power, area, and implementation constraints established with the architecture team.
  • Evaluate representative AI inference workloads across prefill and decode, batch sizes, context lengths, and dense and mixture-of-experts models to identify what limits latency, throughput, and hardware utilization.
  • Communicate findings throughout the design cycle, investigate unexpected results, and update studies as workloads and architectural choices evolve.
  • Develop and extend analytical, transaction-level, and cycle-level models, selecting the level of detail needed to answer each question with useful turnaround time.
  • Maintain reusable models in the native Rust simulator and correlate predictions against RTL simulation, emulation, or silicon measurements as available, with regression coverage and clear documentation of assumptions, limitations, and discrepancies.
  • Own performance modeling for a next-generation inference chip and use analysis to shape architectural decisions before RTL is written.

Desired Qualifications

  • Experience with LLM inference, including attention, KV caches, quantization, mixture-of-experts workloads, and parallelism across multiple chips.
  • A track record of connecting workload behavior and software execution choices to hardware performance.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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