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Broadcom

Designs chips and software for data centers

ASIC DFT Engineer

Hardware Validation & TestingPosted on Nov 11
Full-timeIn-person

About the Job

Requirements

  • Strong DFT architecture and implementation background, including Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, and IEEE 1149.1/1149.6.
  • Proficiency with EDA tools for scan insertion, compression, and ATPG, such as DFT Compiler, TestKompress, TetraMax, and FastScan.
  • Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories including SRAM, CAM, RF, and ROM.
  • Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA.
  • A solid foundation in digital and analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability.
  • Strong problem-solving, root-cause debugging, statistical process control, and data analysis skills for silicon yield and quality improvement.
  • Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations.
  • A Bachelor's degree in Electrical, Electronic, or Computer Engineering and 8+ years of relevant industry experience, or a Master's degree in Electrical, Electronic, or Computer Engineering and 6+ years of relevant industry experience.

Responsibilities

  • Lead DFT programs from chip-level specification through implementation, verification, and product release to production.
  • Participate in all phases of SoC DFT activities for ASIC designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics.
  • Understand company and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC.
  • Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration.
  • Perform ATPG and verification at ASIC/chip level and rapidly bring up ATE test patterns.
  • Collaborate with STA and design integration engineers for timing and design closure.
  • Generate, verify, and debug test vectors before tapeout release.
  • Validate and debug test vectors on ATE during silicon bring-up.
  • Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
  • Interface with customers, physical design teams, and global test engineering and manufacturing teams.
  • Work closely with IP DFT engineers and cross-functional stakeholders.
  • Debug customer-returned parts (RMA) on ATE.
  • Use scripting and automation such as Python, TCL, or C++, applying AI-augmented development to streamline test flows.
  • Develop DFT solutions for advanced process nodes, including 3nm and beyond.
  • Automate DFT and test vector generation flows.

Desired Qualifications

  • Experience with In-Field testing solutions.
  • Experience with ATE silicon bring-up, debugging, and high-speed IP/interface testing, including SerDes, DDR, PCIe, Ethernet, CXL, and Tessent SSN.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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