Senior ASIC Physical Design Engineer

About Positron AI

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.

Role Overview
Contribute to the physical implementation of Positron's AI accelerators from floorplanning through tapeout. Support and help drive implementation methodology while partnering with RTL, synthesis, DFT, package, and backend design services to achieve world-class PPA.

Key Responsibilities

Physical Implementation

• Support floorplanning, macro placement, and power planning across Positron's AI accelerator designs.
• Drive clock tree synthesis, place and route, and routing optimization through to timing closure on assigned blocks.
• Contribute to signal integrity, IR/EM closure, ECO implementation, and metal fill to deliver signoff-quality results.
• Support tapeout signoff for physical implementation deliverables.

Methodology Development

• Contribute to methodology for power grids, power/ground tiles, and bump planning.
• Assist in building congestion analysis and wire estimation approaches to support early floorplan decisions.
• Support partitioning and hierarchical implementation strategies for complex, multi-block designs, under guidance from senior/principal leads.

Tools & Technical Execution

• Execute Innovus-based implementation flows for assigned blocks.
• Apply hands-on expertise across Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre.

Closure & Signoff

• Drive closure across timing, power, area, congestion, DRC, LVS, EM, IR, and yield for owned blocks.

Cross-Functional Partnership

• Partner closely with backend design services to align on implementation strategy and execution.
• Participate in implementation quality reviews.

AI-Enabled Engineering

• Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization.

Required Qualifications

• 5–8 years of experience in physical design, spanning floorplanning through tapeout.
• Experience contributing to one or more advanced-node tapeouts.
• Strong proficiency in Innovus and/or ICC2 implementation flows.
• Solid working knowledge of physical implementation, including floorplanning, clock tree synthesis, timing, and power closure.
• Experience supporting signoff across timing, power, and related quality metrics.

Preferred Qualifications

• Experience with AI accelerator design.
• Familiarity with large SRAM arrays.
• Experience with SerDes and LPDDR interfaces.
• Exposure to chiplet architectures and 2.5D advanced packaging.

Leveling & Scope
This role is posted at the Senior level. We are a growth-oriented organization and are open to discussing scope with candidates whose experience aligns more closely with a more senior track. This job description serves as a focused but generalized overview; specific responsibilities will be tailored to the experience of the final hire.

What Success Looks Like
Success in this role looks like reliable execution on assigned blocks, strong QoR contributions, and growing ownership of implementation methodology as you develop within the team.

Why Join Us?

• Help build the physical implementation methodology for a new class of AI inference accelerators from the ground up.
• Work at the cutting edge of advanced-node design, tackling some of the hardest problems in power, timing, and signal integrity for frontier AI workloads.

Compensation & Benefits
The base salary range for this role is $200,000 – $300,000.

Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.

Benefits & Perks
We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.

Health and wellness

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available

Time off and flexibility

• Unlimited paid time off, so you can truly unplug and recharge
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup

Compensation and future

• Competitive salary and equity
• 401(k) with company matching, eligible from day one

Visa Support
This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.

Equal Opportunity Employer. If you're excited about the role but don't meet every bullet, we'd still love to hear from you.