SiTime

Fabless MEMS timing solutions provider

Senior Layout Design Engineer - Layout Design

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeTokyo, JapanNo salary listedIn-person

About the Job

Requirements

A BA or BS degree in Layout Design or a related field, or equivalent experience.
At least 10 years of layout design experience for analog and full-custom digital blocks.
Experience with TSMC 180 nm, 65 nm, and 22 nm process technologies.
Proficiency with layout editing tools in the Cadence Virtuoso design environment.
Working knowledge of debugging Design Rule Check (DRC), Layout Versus Schematic (LVS), and Electrical Rule Check (ERC) using Cadence PVS or Mentor Calibre.
Conceptual understanding of parasitics, matching, crosstalk, transistor layout-dependent effects, latch-up, IR drop, electromigration (EM), deep N-well, and NTN isolation.
Capability to solve device-matching, electromigration, signal-integrity, and power-distribution problems while meeting area constraints.
Experience in chip-level floor planning and analog block integration.
Experience with chip-level integration, verification, and tape-out.
Ability to lift, push, and pull up to 5 pounds.

Responsibilities

Lead top-level chip planning and perform functional-block-level, block-level, sub-block-level, leaf-cell, and standard-cell custom layouts for CMOS and BiCMOS circuits.
Perform schematic-driven layout and apply design constraints.
Design die-area-efficient layouts according to circuit designer requirements.
Perform block-level or top-level layout design.
Perform floor planning, power-line planning, shielding, and device-matching layout.
Verify layouts and achieve DRC, LVS, and ERC pass results.
Contribute to chip-level routing and layout needs.
Perform chip-level integration, verification, and tape-out.
Support other projects as needed by management.
Train junior layout engineers and offshore layout contractors.
Contribute to common best practices and workflows across all sites.
Contribute to processes and procedures that achieve high layout quality.
Interface remotely with local and global design and layout teams across multiple design centers and time zones.
Review and coordinate work content performed by offshore layout designers.

Desired Qualifications

Ability to use productivity-enhancing tools and design scripts to further automate tasks.
Attention to detail, organization, and accuracy in producing efficient layout techniques.
A track record of delivering work on time.
Ability to work well with others in a fast-paced, collaborative team environment.

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality

Responsibilities:

Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
Perform schematic-driven layout and design constraints
Design die-area efficient layouts according to circuit designer requirements
Perform block or top-level layout designs
Perform floor-planning, power line planning, shielding, and device-matching layout
Verify layouts. Pass DRC, LVS, and ERC
Contribute to various chip-level routing and layout needs
Perform chip level integration, verifications, and tape-out
Support other projects as needed by management
Train junior layout engineers and offshore layout contractors
Contribute to developing common best practices and workflow across all sites
Contribute to build process and procedures to achieve high layout quality

Qualifications & Requirements:

BA/BS Degree in Layout Design or related field or equivalent experience
10 years’ experience with layout design for analog and full-custom digital blocks
Experience TSMC 180nm, 65nm, 22nm process technologies
Proficient in using layout editing tools in the Cadence Virtuoso design environment
Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
Experience in chip‐level floor planning and analog block integration
Experience chip level integration, verifications, and tape-out
Ability to use productivity‐enhancing tools and design scripts to further automate tasks is also desirable
Must be able to lift, push, and pull up to 5 lbs

Desired Characteristics & Attributes:

Attention to detail, organized, accurate and can produce efficient layout techniques
Has a good track record of on time work delivery
Has a self-motivated, team player with good communication skills
Ability to work well with others in a fast-paced collaborative team environment

Compensation Range:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is committed to providing equal employment opportunities to all employees and applicants. Employment decisions are based on qualifications, merit, and business needs. We do not discriminate on the basis of any characteristic protected by applicable law.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

About the Company

SiTime

Fabless MEMS timing solutions provider

SiTime designs MEMS-based timing solutions (oscillators, network synchronizers, and jitter cleaners) as a fabless semiconductor company. MEMS resonators on silicon replace quartz to generate precise clocks and synchronize networks, with manufacturing handled by third-party foundries. The approach offers smaller size, lower power consumption, and better temperature stability, supported by scalable, design-focused development rather than in-house fabrication. Its goal is to expand MEMS timing adoption across automotive, industrial, IoT, mobile, aerospace, and telecom markets worldwide.

Company size: 501-1,000
Company stage: IPO
Headquarters: Santa Clara, CA
Founded: 2005

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