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Analog Bits

Mixed-signal IP for power management

CMOS Mixed-Signal Circuit Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timePrague, CzechiaNo salary listed

About the Job

Requirements

  • A strong foundation in analog and digital circuit design is required.
  • Hands-on experience with advanced CMOS technologies is required.
  • Skilled knowledge of bandgap references and amplifiers for PVT sensors is required.
  • Skilled knowledge of high-sensitivity and precision sense amplifiers is required.
  • Skilled knowledge of I/O and interface circuit design is required.
  • Skilled knowledge of low-jitter and spread-spectrum phase-locked loops, including LC-based architectures, is required.
  • A Master’s degree or higher in Electrical Engineering or a related field is required.

Responsibilities

  • Design low-power, high-performance clocking, sensor, power regulation, and interconnect circuits on advanced CMOS nodes, including FinFETs and GAA.
  • Develop and verify mixed-signal, analog, and digital circuit blocks.
  • Guide layout implementation and perform post-layout simulations and analysis.
  • Participate in design reviews and generate technical documentation.
  • Collaborate with quality assurance and product engineering to support production release.
  • Support silicon bring-up, laboratory debugging, and performance validation.
  • Provide technical support to global customers during pre-sales and post-sales phases.

About the Company

Analog Bits

Mixed-signal IP for power management

Analog Bits provides mixed-signal IP (intellectual property) for intelligent energy and power management used in semiconductor chips. Its products include precision clocking macros (PLLs, oscillators), sensors to monitor temperature and voltage, and power-control blocks (like LDOs), plus integrated or separate bandgap and ADC IP. A key feature is the patented pinless/core-powered IP, which lets IP blocks be placed anywhere on a chip without external power pins while preserving analog performance, enabling easier, more reliable integration into SoCs across major foundries. The company has a 30+ year track record with silicon-proven IP across processes from 0.35 micron to 2nm and a broad portfolio designed to improve performance, cost, and reliability in applications ranging from consumer electronics and edge AI to automotive and aerospace. Its goal is to provide differentiated, easy-to-integrate IP that reduces risk and accelerates power and energy management in modern chips.

Company size
11-50
Company stage
Not listed
Total funding
Not listed
Headquarters
Sunnyvale, CA
Founded
1995

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