A

Astera Labs

Designs chips that connect data center systems

Senior Principal Program Manager - ASIC Design

Program ManagementConfirmed live in the last 24 hours
Full-timeToronto, ON, CanadaIn-person

About the Job

Requirements

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.
  • Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
  • Experience with advanced process nodes and high-performance ASIC/SoC development.
  • Strong understanding of ASIC development milestones from product requirements through final GDS handoff.
  • Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.
  • Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.
  • Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.

Responsibilities

  • Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
  • Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
  • Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.
  • Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
  • Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
  • Partner with Post-Silicon PM and Validation teams to incorporate feedback from post-silicon bring-up, including bug reports and silicon issues.
  • Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.
  • Communicate program health, risks, dependencies, and decisions to engineering teams, senior leaders, executives, and external partners.
  • Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, and lead continuous improvement.

Desired Qualifications

  • Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
  • Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

Recently Posted Jobs

Explore more opportunities at Astera Labs

See more jobs