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Micron Technology

Makes memory and storage chips for AI and PCs

Design / Design for Test Director

Engineering LeadershipPosted on Nov 9
Full-timeAvezzano, ItalyIn-person

About the Job

Requirements

  • An M.S. or Ph.D. in Electrical Engineering, Electronics, Computer Engineering, or a related field.
  • Significant experience in semiconductor design, design for test (DFT), product test, or silicon validation, including leadership of sophisticated engineering programs and teams.
  • Demonstrated success defining strategy and delivering complex products from concept through tape-out, silicon validation, and large-scale manufacturing.
  • Deep knowledge of NAND design, verification, DFT principles, test architecture, coverage analysis, silicon debug, and semiconductor manufacturing flows.
  • Proven people leadership, including organization building, talent development, performance management, and leading through other managers or senior technical leaders.
  • Strong multi-functional influence, executive communication, technical decision-making, and program execution skills in a global environment.
  • A solid understanding of artificial intelligence/machine learning and data-analytics techniques and their practical application to semiconductor design, test, or manufacturing.
  • Proficiency with engineering automation and working knowledge of scripting or programming languages such as Python and C/C++.

Responsibilities

  • Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations; anticipate future requirements and establish scalable architectures, methodologies, technical priorities, success metrics, and governance aligned with quality, cost, performance, and schedule objectives.
  • Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out; lead scalable testability, diagnostic, design-for-debug, and embedded test solutions across digital logic and custom circuits, ensuring predictable delivery and clear coverage, test-time, area, power, quality, and execution targets.
  • Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs; work with Product Engineering, Test, Probe, Failure Analysis, Quality, Technology Development, and Manufacturing through silicon bring-up, qualification, and high-volume production to achieve quality, coverage, yield, reliability, test-time, cost, and time-to-market objectives.
  • Drive reusable methodologies, automation, and DFT and design-for-debug innovation; strengthen simulation-to-silicon correlation, diagnostics, and root-cause resolution, with measurable improvements in debug efficiency, silicon learning, test quality, test time, yield learning, product cost, and time to market.
  • Build, develop, and inspire a high-performing global DFT organization; develop managers and senior technical leaders through mentoring, talent development, performance management, succession planning, and career growth.
  • Allocate priorities and resources across complex programs, communicate strategy, plans, decisions, risks, and results to senior partners, and sustain technical depth, AI and data skills, leadership capability, engagement, and retention within an inclusive, high-trust engineering culture.
  • Deploy data-driven and AI-assisted solutions for test-pattern and test-flow optimization, fail diagnosis and root-cause analysis, yield prediction, coverage analytics, and test-time reduction.
  • Establish reusable AI-enabled DFT, diagnostic, and analytics workflows; measure gains in debug time, test time, yield learning, engineering productivity, quality, and execution speed.
  • Build AI and data-analytics capabilities across the team and partner across functions to evaluate, adopt, and scale emerging tools and methodologies supporting future NAND technology generations.

Desired Qualifications

  • Experience with NAND Flash or other non-volatile memory technologies and their design, test, reliability, and manufacturing challenges.
  • Experience with memory test algorithms, embedded self-test/diagnostics, custom-circuit DFT, firmware-to-hardware test interfaces, and production test optimization.
  • Hands-on experience deploying AI, machine learning, or sophisticated analytics in production environments for design verification, coverage, silicon debug, yield, or test optimization.
  • A track record of improving test quality, yield learning, test time, product cost, or time to market through methodology and interpersonal innovation.
  • Experience leading geographically distributed teams and collaborating with external EDA, IP, equipment, or technology partners.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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