Synopsys

EDA software for chip design

ASIC Digital Design Senior Engineer

Hardware Validation & TestingPosted on Nov 13

Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

Engineering degree or postgraduate qualification (B.Tech or M.Tech) and 2–5 years of verification experience.
Hands-on coding experience in Verilog, SystemVerilog, and a methodology such as UVM.
Experience with SVA assertions, functional coverage, and coverage-driven verification.
Strong debugging skills using Verdi, including waveform, transaction- and protocol-level analysis, and root-cause analysis.
Proficiency in one or more structured programming languages such as C, C++, or Python.
Strong analytical thinking, problem-solving, debugging skills, and attention to detail.
Ability to collaborate across design, architecture, and validation teams and drive issues to resolution.
Effective written and oral communication and interpersonal skills for working in a geographically distributed team.
Motivation, curiosity, and a self-driven approach to learning.

Responsibilities

Contribute to end-to-end verification of subsystems with high-speed interconnect IPs, including controllers and PHY IP related to Ethernet, UFS, UniPro, USB, or M-PHY, from test planning through coverage closure and sign-off.
Develop and use verification environments for synthesizable IP cores and perform verification tasks on those cores.
Understand compliance testing standards and build simulation-based compliance test suites.
Develop SystemVerilog and Verilog testbenches and test cases; run regressions, analyze coverage, and debug failures using methodologies such as UVM and formal verification.
Perform test planning, unit-level and system-level test-environment coding, test-case coding and debugging, controller-PHY IP interoperability testing, and regression management.
Work with AI models and build agentic workflows for verification, including automated testbench creation, test planning, coverage analysis, and closure.
Collaborate across design, architecture, and validation teams and drive issues to resolution.

Desired Qualifications

Controller-PHY integration or interoperability simulation experience.
Prior experience using industry-standard VIP.
Experience building AI agents, agentic workflows, and AI-driven engineering automation.

Job Description and Requirements

The Synopsys Digital IP R&D team is hiring experienced ASIC/IP Verification Engineers (2 to 5 years) to work on advanced connectivity protocols, including Ethernet / UFS / UniPro / USB / MPhy, across commercial, enterprise, and automotive applications.

Job Role

What You'll Be Doing:

Be part of the Synopsys IP Verification R&D team at our Bangalore R&D Center, working closely with the RTL design team within a global team of expert Verification Engineers
Contribute to end-to-end verification of subsystems with high-speed interconnect IPs, including one or more of controllers and Phy IP related to protocols such as Ethernet / UFS / UniPro / USB / MPhy, from test planning to coverage closure and sign-off
Develop and use state-of-the-art verification environments for the Synopsys IP family of synthesizable cores, and perform verification tasks on these IP cores
Understand compliance testing standards and build simulation-based compliance test suites
Develop SystemVerilog/Verilog testbenches and test cases; run regressions, analyze coverage, and debug failures using methodologies such as UVM and formal verification
Cover test planning, unit-level and system-level test environment coding, test case coding and debugging, Controller-PHY IP interoperability testing, and regression management
Beyond traditional verification, you’ll have the opportunity to work with frontier AI models and build agentic workflows for verification, from automated testbench creation and test planning to coverage analysis and closure.
Contribute to IP development used in high-performance computing, communications, servers, consumer devices, and automotive applications that power the technologies of tomorrow
Collaborate across design, architecture, and validation teams and drive issues to resolution

Requirements:

What You'll Need:

Engineering degree / Post graduation (B.Tech / M.Tech) with 2–5 years of verification experience
Hands on experience with coding in Verilog, System Verilog and methodology such as UVM
Controller–PHY integration / interoperability simulation experience is a strong plus
Prior experience in usage of industry standard VIP is a definite advantage
Experience with SVA assertions, functional coverage, and coverage-driven verification
Strong debug skills using Verdi (waveform + transaction/protocol-level analysis, RCA)
Proficiency in one or more structured programming languages such as C, C++, Python.
Experience building AI agents, agentic workflows, and AI-driven engineering automation will be a distinct advantage
Strong analytical thinking, problem-solving ability, debugging skills, and attention to detail
Ability to collaborate across design/architecture/validation teams and drive issues to resolution
Effective written and oral communication is a must; Good interpersonal skills for working in a geographically distributed team
High levels of motivation, curiosity, and a self-driven approach to learning

If you are interested in verifying production-quality IP that ships into real silicon and directly impacts first pass-silicon success, please connect or reach out.

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

Working Model: Onsite; Full-Time, In-office 4-5 days per week

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size: 10,001+
Company stage: IPO
Headquarters: Sunnyvale, CA
Founded: 1986

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