Senior CPLD Engineer

At Jabil (NYSE: JBL), we are proud to be a trusted partner for the world's top brands, offering comprehensive engineering, supply chain, and manufacturing solutions. With 60 years of experience across industries and a vast network of over 100 sites worldwide, Jabil combines global reach with local expertise to deliver both scalable and customized solutions. Our commitment extends beyond business success as we strive to build sustainable processes that minimize environmental impact and foster vibrant and diverse communities around the globe.

JOB SUMMARY

Under the guidance of management, develop new engineering designs of basic to moderate complexity. Gather design requirements and recommend implementation steps for basic to moderate reference designs, including modifications to existing products. Perform and analyze circuit designs of basic to moderate complexity, escalating more complex issues to management or senior team members. Develop subsystem architecture under the direction of a Lead Engineer or above.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Work closely with Hardware, BIOS, BMC, and Firmware teams for CPLD / FPGA design, validation, and maintenance.
• Develop Server / Storage production power on sequence control logic by CPLD / FPGA.
• Implement new technology and design concept in CPLD / FPGA.
• Design test plan, development specifications, and issue tracking.

JOB QUALIFICATIONS

KNOWLEDGE REQUIREMENTS

TECHNICAL KNOWLEDGE & SKILLS

• 5+ years of working experience in CPLD / FPGA development.
• Familiar with CPLD / FPGA design and Verilog/VHDL coding.
• Experience in I2C, SPI, UART, and SGPIO protocols.
• Experience in RTL coding and simulation.
• Building in CPLDs and FPGAs, including coding practice, RTL coding standards, using Git, building test benches, etc.
• Familiar with System Verilog, Git, server product, and UVM is a plus.

NON-TECHNICAL KNOWLEDGE & SKILLS

• Influence others and share best practices.
• Effectively communicate with a good understanding of English.
• Work as part of a global team.

EDUCATION & EXPERIENCE REQUIREMENTS

• Electrical Engineering Degree (BSEE/MSEE or equivalent experience)
• 5+ years of experience in CPLD / FPGA design or another key competency.
• Or an equivalent combination of education, training, or experience.

Domestic and international travel is required (within 1 month)

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Jabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identity, age, disability, genetic information, veteran status, or any other characteristic protected by law.

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