FPGA Development Tools Engineer
No salary listed
Mid, Senior
Bachelor's, Master's, PhD
George Town, Penang, Malaysia
In Person
Hardware EngineeringHardware Validation & Testing
About the job
Requirements
- A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Four to five years of relevant experience.
- A strong foundation in digital design principles, including combinational and sequential logic, clocking, resets, and pipelining.
- Experience with FPGA or ASIC flows, including RTL using Verilog, SystemVerilog, or VHDL; synthesis; static timing analysis; and SDC constraints.
- Proficiency in Tcl or Python and a working foundation in C++ for developing or debugging hardware or device models.
- Familiarity with Linux development environments and build workflows.
- Ability to interpret tool logs and timing reports.
- Effective written communication for documentation and clear defect reporting.
Responsibilities
- Develop comprehensive test plans for device and simulation model validation across Quartus Prime components.
- Execute targeted and regression tests across multiple FPGA device families, configurations, and corner cases.
- Ensure verification coverage aligns with design intent and release quality goals.
- Build and run end-to-end Quartus projects to exercise synthesis, fitting, and simulation signoff on representative designs.
- Maintain golden reference results and compare and triage deltas in quality of results, performance, resource utilization, and warnings or errors.
- Package and maintain reproducible test kits and reference designs.
- Create and maintain automation and modeling tools using C++, Tcl, Python, and Bash for test generation, execution, log mining, and results reporting.
- Develop and maintain C++ device model libraries representing FPGA architecture blocks such as DSP and memory used by synthesis and simulation flows.
- Integrate tests and model validation into continuous integration pipelines, including pass/fail gates and artifact tracking.
- Develop utilities to parameterize devices, architectural variants, corners, and random seeds for coverage expansion.
- Analyze failures across synthesis, fitter, and device models; isolate root causes across RTL, constraints, tool behavior, and C++ model implementations.
- Collaborate with modeling, device, and software teams to validate fixes and prevent regressions.
- Track and improve quality metrics, including pass rate, coverage, and defect density.
- Author and maintain test plans, runbooks, and user guides for test environments.
- Contribute to checklists and acceptance criteria for device and model signoff.
- Help improve the validation process for better scalability and repeatability.
Desired Qualifications
- Experience developing or maintaining C++ libraries for hardware, architectural, or device modeling, such as DSP, memory, or timing models.
- Experience with Altera Quartus Prime Lite, Standard, or Pro, including TimeQuest and basic fitter concepts.
- Hands-on experience with Git and continuous integration systems such as Jenkins or GitLab CI.
- Familiarity with device concepts such as speed grades, PVT corners, IO standards, and clocking networks.
- Basic understanding of timing signoff concepts, including clocks, generated clocks, I/O delays, false paths, and multicycle paths.
- Coursework or projects involving FPGA boards, EDA tools, or regression test environments.
About the company
Altera designs and manufactures Field-Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) and sells design software. Its programmable logic devices let customers configure hardware after manufacturing to fit specific applications, supported by toolchains for hardware design and deployment. It serves automotive, communications, aerospace, and expanding sectors like AI, cloud, and edge computing, focusing on flexible, high-performance processing solutions. As an independent company after separating from Intel, its goal is to help customers bring customized hardware to market quickly by providing both configurable silicon and the software to design for it.
Company Size
N/A
Company Stage
Acquired
Total Funding
$21.2B
Headquarters
San Jose, California
Founded
1983
Simplify's Take
What believers are saying
- September 2026 board additions and Nishit Sahay’s CIO hire strengthen execution.
- September 2026 PQC, DDR5, and Agilex updates improve product relevance immediately.
- October 2026 hiring remains broad, signaling expansion across engineering, sales, and operations.
What critics are saying
- Altera filed a confidential S-1 on September 15, 2026; IPO demand decides financing.
- Intel still owns 49%, keeping governance tension and strategic ambiguity alive.
- NVIDIA, AMD, and custom ASICs compress FPGA adoption; one weak quarter can freeze growth.
What makes Altera unique
- Altera remains the largest pure-play FPGA provider after Silver Lake’s 2025 separation.
- Agilex 3, 5, and 7 add PQC security, DDR5, and low-latency connectivity.
- Rutronik, Riverlane, and Pantherun partnerships extend Altera’s reach into Europe, quantum, and networking.
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Benefits
- Performance Bonus