A

Astera Labs

Designs chips that connect data center systems

Physical Design Engineering Director

Full-Time
CA$200k - CA$250k+ Discretionary bonus + Incentives
Expert
Bachelor's, Master's
Toronto, ON, Canada
In PersonFully on-site at the Toronto location.
Engineering ManagementEngineering Leadership

About the job

Requirements
  • A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required; a Master's degree is preferred.
  • At least 15 years of experience in physical design implementation of complex SoCs at advanced nodes of 7nm and below.
  • At least 5 years of experience leading teams or projects, with demonstrated ability to mentor and develop engineers.
  • Hands-on expertise across the physical design flow, including synthesis, place-and-route, clock tree synthesis, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
  • Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
  • Strong scripting ability in Tcl, Python, and/or Perl.
  • Ability to prioritize a dynamic task list, plan and prepare for customer meetings in advance, and work with minimal guidance.
  • Experience with Cadence and/or Synopsys physical design tools and flows.
Responsibilities
  • Build, lead, and mentor a physical design team, owning physical design execution and team development for Signal Connectivity Group products.
  • Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
  • Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
  • Work with IP vendors on RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
  • Drive team execution, hiring, career development, and sprint planning for the Toronto physical design team.
  • Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
  • Coordinate with global physical design teams in San Jose, Irvine, and Bangalore to ensure consistent methodology and design quality.
Desired Qualifications
  • Deep understanding of high-speed SerDes physical layers, including equalization, CDR, and signal integrity considerations that impact physical design.
  • Knowledge of physical-layer timing challenges specific to high-speed serial interfaces.
  • Track record of building and scaling physical design teams through multiple tapeouts.
  • Knowledge of agentic AI solutions for EDA automation.

About the company

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company Size

501-1,000

Company Stage

IPO

Headquarters

San Jose, CA

Founded

2017

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Simplify's Take

What believers are saying

  • Revenue grew rapidly: Astera's August 2026 release reported preliminary Q2 revenue of $392.4 million, up 104% yearly.
  • Memory products broadened: Astera announced three new Leo controllers in September 2026, with the family sampling to hyperscalers.
  • Managers have a published pay band: Astera's live San Jose Ethernet applications role lists base pay of $158,400 to $230,000.

What critics are saying

  • Revenue is concentrated: Astera's February 2026 filing says three end customers generated 86% of fiscal 2025 revenue.
  • Chip production has one foundry: Astera's annual filing says TSMC fabricates all its integrated circuits.
  • Customer support involves travel: Astera's live San Jose Ethernet applications manager role requires travel within the US and Asia.

What makes Astera Labs unique

  • Hardware health is visible: Astera's COSMOS software monitors link performance, temperature and signal quality across systems.
  • Switches connect large clusters: Astera's Scorpio X-Series supports up to 80 accelerators per switch across 320 data lanes.
  • Integration gets tested early: Astera's Cloud-Scale Interop Lab checks switches against diverse PCIe hosts and endpoints.

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Benefits

  • 401(k) Retirement Plan
  • Flexible Work Hours

Growth & Insights and Company News

6 month growth

5%

1 year growth

2%

2 year growth

3%
Yahoo Finance
Nov 2nd, 2026
Astera Labs needs Q4 guide of $648M–$668M to hold $1.91B 2026 forecast after 11% drop

Astera Labs shares fell 11% on Friday, October 30, nearly four times the Nasdaq Composite's 2.9% drop. The fall followed weak search results at Alphabet, heavier AI spending signals from Amazon, and a cash burn warning from Intel, none of which involved Astera. The company reports third-quarter results after the close on November 3. To support analysts' 2026 revenue estimate of $1.91 billion, it needs a fourth-quarter guide of $648 million to $668 million. Gross margin is the other test. Management guided to about 72% for the third quarter, down from 76.3% in the first, with roughly half of the slide from a non-cash charge tied to a warrant given to Amazon and the rest from more hardware in the mix. The stock trades at 46 times forward earnings, against a one-year average of 72 times.

Yahoo Finance
Oct 20th, 2026
Astera Labs, valued at $50B, doubles revenue but trades at 178x earnings: S&P 500 ready?

Astera Labs, which makes chips and hardware that move data inside AI data centres, is emerging as a contender for the S&P 500 Index. The company, valued at roughly $50 billion, went public in March 2024 and is now profitable. Revenue rose about 104.5% over the past year as hyperscalers spent heavily on AI infrastructure. The company recently launched its Aries 7 portfolio of high-speed links. The stock trades near 178 times trailing earnings and about 56 times expected profit next year. Northland downgraded it on valuation, and the shares sit well below their $499 high. Astera also relies on a small group of hyperscale buyers. Hedge fund holders rose to 73 at the end of the second quarter of 2026, from 53 the quarter before.

Yahoo Finance
Oct 20th, 2026
Micron up 350%, but SK Hynix, Sandisk and Astera Labs may offer faster growth

Micron's stock has risen about 350% in a year, but three rival memory stocks may offer better value, according to one analyst view. SK Hynix posted second-quarter revenue of 79.3 trillion Korean won (about $54.9 billion), up 257% year over year and 51% sequentially. Micron grew 31% sequentially. SK Hynix also has a lower market cap and a more attractive P/E ratio. Sandisk shares have surged more than 800% in a year. It expects fiscal 2027 first-quarter revenue of up to $10.8 billion, or 20.4% sequential growth. Astera Labs, which builds rack-scale AI infrastructure, more than doubled its second-quarter sales. It guides to $550 million in third-quarter sales at the midpoint, a 40.2% sequential rise.

Yahoo Finance
Oct 17th, 2026
Northland downgrades Astera Labs on valuation despite $540M–$560M Q3 revenue guidance

Northland Capital Markets downgraded Astera Labs to "Market Perform" from "Outperform" on October 9, citing valuation concerns, even though it expects earnings to rise. Analyst Gus Richard said shares had passed Northland's earlier target, but he still sees estimates climbing as the Scorpio X AI switch ramps up. Astera expects third-quarter revenue of $540 million to $560 million, up from a record $392.4 million in the second quarter. Non-GAAP earnings per share are guided to $1.16 to $1.21, against $0.80 in the previous quarter. The growth leans on one lead customer, though more than 10 customers are engaged on Scorpio X. Shares closed at $285.82 on October 16, about 43% below their June peak of $499.48. Fubon Securities recently began coverage with a "Buy" rating and a $500 price target.

Converge! Network Digest
Oct 12th, 2026
Astera Labs' Orion rack supports Up to 160 accelerators.

Astera Labs' Orion rack supports Up to 160 accelerators. Astera Labs introduces Orion, a compute-agnostic rack-scale AI inference architecture supporting up to 160 accelerators per pod through a 320-lane PCIe fabric, modular reference designs, and COSMOS management software. Astera Labs (Nasdaq: ALAB) introduced Orion, a compute-agnostic rack-scale reference architecture designed to support AI inference deployments with up to 160 accelerators per pod. Announced at the 2026 Open Compute Project Global Summit in San Jose, Orion combines a high-radix, 320-lane PCIe switching fabric with modular compute, memory and connectivity subsystems. Operators can select GPUs, CPUs and other accelerators based on workload requirements, availability and cost rather than committing to a single compute platform. Orion comprises six production-grade reference designs covering the complete rack, compute trays, fabric trays, memory trays, link boards and compute boards. The designs aim to reduce integration and validation work for OEMs and ODMs while allowing different accelerator configurations within a common infrastructure. COSMOS Rack Manager and COSMOS Fabric Manager provide orchestration, telemetry, diagnostics and fabric management. Astera Labs will design and validate the reference architecture and subsystems rather than manufacture complete racks. OEM and ODM partners are expected to offer Orion-based systems beginning in Q1 2027. At OCP Global Summit October 12-15, Astera Labs is demonstrating a powered Orion rack with interchangeable, pre-validated compute trays. | ORION - KEY FACTS | | - Compute-agnostic architecture with interchangeable CPU/GPU options | | - Up to 160 accelerators per pod; 320-lane PCIe switch fabric | | - Six reference designs: rack, compute tray, fabric tray, memory tray, link board and compute board | | - COSMOS Rack Manager and Fabric Manager | | - UALink on roadmap; OEM/ODM availability targeted Q1 2027 | Analysis: Orion extends Astera Labs beyond individual connectivity components toward defining how those components are integrated into AI infrastructure. Its existing portfolio includes Scorpio Smart Fabric Switches, Aries signal conditioners, Leo Smart Memory Controllers, Taurus Ethernet connectivity and COSMOS management software. The announcement does not specify that every Orion configuration uses every product family. The PCIe fabric is intended to accommodate heterogeneous inference workloads. Actual throughput will depend on PCIe generation, topology, aggregate bandwidth, accelerator and memory configurations, software and workload characteristics. Astera Labs has not disclosed independently verified benchmarks establishing improvements in tokens per second or tokens per dollar against specific competing systems. Dedicated memory trays could help operators configure memory resources separately from compute, relevant to model weights and key-value caches. Benefits depend on memory access mechanisms, accelerator compatibility, latency and bandwidth. For neoclouds, modular infrastructure may reduce exposure to accelerator procurement constraints, although actual capital savings depend on configuration, utilization and integration costs. UALink is on Orion's future interconnect roadmap, not a confirmed feature of the initial release. Key commercial milestones include naming OEM and ODM partners, supported accelerators, customer deployments, pricing and measured inference performance. | ASTERA LABS | COMPANY PROFILE | | Headquarters | San Jose, California | | Ticker | NASDAQ: ALAB | | Products | Scorpio, Aries, Leo, Taurus, COSMOS, Orion | | Technology | PCIe, CXL, Ethernet, NVLink Fusion; UALink roadmap | | Markets | Hyperscalers, neoclouds, enterprise AI | | Website | asteralabs.com | | RELATED CONVERGE DIGEST COVERAGE | | For related reporting on Astera Labs PCIe, CXL, Scorpio, Aries and Leo technologies, see the Converge Digest archive: Astera Labs coverage. Individual article links from the draft have not been independently verified. | Converge Digest is tracking AI infrastructure developments. Follow ongoing coverage at Converge Digest AI Infrastructure. Help others discover this reporting. Editorial responsibility Jim Carroll. Editor & Publisher Every article published by Converge Digest is researched, curated, fact-checked and editorially reviewed by Jim Carroll, Editor & Publisher. AI-assisted drafting may be used to accelerate production, but all content is reviewed, refined and approved prior to publication. Builders & Visionaries The people who opened the doors to the networks Converge Digest run today. Which of these co-founded Astera Labs? On this day. October 12 From 25 years of the Converge Digest archive.