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Micron Technology

Makes memory and storage chips for AI and PCs

Senior CAD Engineer - Physical Verification

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeIn-person

About the Job

Requirements

  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
  • At least 5 years of industry experience in CAD, EDA, or semiconductor design.
  • Experience with design rule checking (DRC), layout versus schematic (LVS) physical verification, integrated-circuit layout, and process design rules.
  • Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
  • Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting.
  • Solid CMOS and VLSI fundamentals, clear communication, and practical debugging skills across global teams.

Responsibilities

  • Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
  • Develop, debug, qualify, and release Siemens Calibre design rule checking (DRC) and layout versus schematic (LVS) rule decks using Standard Verification Rule Format (SVRF).
  • Translate process design rules into verification checks, and define the test cases, coverage criteria, and regression methods that qualify them.
  • Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
  • Guide design teams on verification methodologies, waivers, and debugging, and provide training, documentation, and production support.
  • Evaluate EDA technologies that improve verification quality, performance, and capacity.
  • Automate verification setup, execution, and reporting, including AI-assisted analysis and debugging.
  • Lead technical projects and contribute to the physical verification roadmap.

Desired Qualifications

  • Experience developing and qualifying Calibre DRC and LVS rule decks in SVRF, using nmDRC, nmLVS, and Results Viewing Environment (RVE).
  • Knowledge of layout-dependent effects and electrical rule checking (ERC), programmable ERC (PERC), antenna, and density checks.
  • Experience optimizing rule-deck coverage, runtime, and memory use.
  • Experience with Cadence Virtuoso, SKILL, or Cadence physical verification tools.
  • Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
  • Experience with source control, automated testing, and release management.
  • Knowledge of DRAM, HBM, NAND, or emerging memory development.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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