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Synopsys

EDA software for chip design

Analog Design Principal Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeNo salary listed

About the Job

Requirements

  • At least 8 years of CMOS analog/mixed-signal design experience, with a MASc, PhD, or Bachelor's degree plus experience.
  • Expertise in transistor-level design and SerDes circuits.
  • Hands-on experience with FinFET layout optimization.
  • Proficiency with SPICE simulators, electronic design automation tools, and scripting such as Python and TCL.
  • Knowledge of reliability and electrostatic discharge design techniques.

Responsibilities

  • Review SerDes standards and develop analog sub-block specifications.
  • Design and optimize high-speed analog circuits.
  • Propose and execute verification strategies.
  • Collaborate with layout and digital teams.
  • Present simulation results to peers and customers.
  • Mentor junior engineers and document designs.
  • Advance the silicon IP portfolio.
  • Enable faster, lower-risk product launches for customers.
  • Push performance boundaries in datacenter, automotive, and communications applications.
  • Promote best practices in design and mentoring.
  • Strengthen cross-functional collaboration.
  • Enhance overall product quality and reliability.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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