ASIC Failure Analysis Engineer

The application window is expected to close on: 12/03/2026<p><b>This is an onsite position in San Jose, California, United States.</b><br />NOTE: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.</p><p><br /><br /></p><h2 style="color:!important"><span style="color:#07182d">Meet the Team</span></h2><p style="color:!important"><span style="color:#07182d">As a Failure Analysis Engineer, you will be part of the Quality and Reliability group, performing failure analysis of ASIC products. Should have a passion for problem solving and a strong technical background in semiconductor failure analysis techniques and root cause analysis.</span></p><p><span style="color:#07182d"><br /></span></p><h2 style="color:!important"><span style="color:#07182d">Your Impact</span></h2><p style="color:!important"><span style="color:#07182d">This role will require high level of collaboration and interaction with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering and Foundry Engineering teams. The successful candidate must be able to work well within a team and have excellent communication and organizational skills with customers and vendors. Experience with a variety of semiconductor failure analysis techniques and test equipment is required, along with the ability to interpret results and provide clear guidance on causes of failure. Responsibilities include:</span></p><ul><li style="color:!important"><span style="color:#07182d">Conduct root cause failure analysis of silicon product reliability test and field failures and propose corrective actions.</span></li><li style="color:!important"><span style="color:#07182d">Develop and implement standard processes for failure analysis using all types of FA equipment.</span></li><li style="color:!important"><span style="color:#07182d">Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way.</span></li><li style="color:!important"><span style="color:#07182d">Document and report failure analysis results to management.</span></li><li style="color:!important"><span style="color:#07182d">Function as a technical resource for failure analysis questions.</span></li><li style="color:!important"><span style="color:#07182d">Develop and maintain relationships with FA service and equipment vendors.</span></li><li style="color:!important"><span style="color:#07182d">Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies, while providing fault isolation, identification, and characterization for yield/reliability failures.</span></li></ul><p><span style="color:#07182d"><br /></span></p><h2 style="color:!important"><span style="color:#07182d">Minimum Qualifications</span></h2><ul><li style="color:!important"><span style="color:#07182d">Bachelor's degree in Electrical/Electronics Engineering or related required. Master's degree preferred.</span></li><li style="color:!important"><span style="color:#07182d">5+ years of experience in semiconductor failure analysis field.</span></li><li style="color:!important"><span style="color:#07182d">Previous background writing and executing FA plans and interpret results from FA techniques such as cross section, X-ray, CSAM, TDR, FIB, SEM, and TEM, IR/EMMI/OBIRCH.</span></li><li style="color:!important"><span style="color:#07182d">Validated ability to specify hardware and implement set up for dynamic FA using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).</span></li><li style="color:!important"><span style="color:#07182d">Prior experience of fault isolation techniques using ATE, Scan/ATPG, MBIST to identify, isolate and characterize device-level faults.</span></li></ul><p><span style="color:#07182d"><br /></span></p><h2 style="color:!important"><span style="color:#07182d">Preferred Qualifications</span></h2><ul><li style="color:!important"><span style="color:#07182d">Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging).</span></li><li style="color:!important"><span style="color:#07182d">Good understanding of transistor function/basic electronics, semiconductor device physics and behavior under various operating conditions.</span></li><li style="color:!important"><span style="color:#07182d">Proficient in ATE docked dynamic fault isolation using LVP, LVI/SMI, LADA, TIVA techniques..</span></li><li style="color:!important"><span style="color:#07182d">Knowledge of JEDEC IC Qualification tests and requirements is beneficial.</span></li><li style="color:!important"><span style="color:#07182d">Applied experience driving physical failure analysis with suppliers.</span></li></ul><br /><p>siops</p><p></p><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><p></p><h1>Message to applicants applying to work in the U.S. and/or Canada:</h1><p></p>The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.<p></p><p>Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.</p><p></p><p>U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.  Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.</p><p></p><p>U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:</p><ul><li><p>10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees</p></li><li><p>1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco</p></li><li><p>Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees</p></li><li><p>Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)</p></li><li><p>80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next</p></li><li><p>Additional paid time away may be requested to deal with critical or emergency issues for family members</p></li><li><p>Optional 10 paid days per full calendar year to volunteer</p></li></ul><p></p><p>For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.</p><p></p><p>Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:</p><ul><li><p>.75% of incentive target for each 1% of revenue attainment up to 50% of quota;</p></li><li><p>1.5% of incentive target for each 1% of attainment between 50% and 75%;</p></li><li><p>1% of incentive target for each 1% of attainment between 75% and 100%; and</p></li><li><p>Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.</p></li></ul><p></p><p>For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.</p><p></p><p>The applicable full salary ranges for this position, by specific state, are listed below:</p><p></p><p>New York City Metro Area:</p>$155,000.00 - $256,000.00<p></p><p>Non-Metro New York state & Washington state:</p>$138,100.00 - $227,900.00<p></p><p>* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.</p><p>** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.</p>