ASIC Physical Design CAD Engineer

<p><br /><b><span>Job Description</span></b></p><p><span>Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team.</span></p><p><br /><b><span>Meet the Team</span></b></p><p><span>You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts.</span></p><p><span>As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation.</span></p><p><span>Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.</span></p><p><span>We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.</span></p><p><span>Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!</span></p><p></p><p><b><span>Your Impact</span></b></p><p><span>You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.</span></p><p><span>Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.</span></p><p><span>You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.</span></p><p></p><h2><span>Minimum Qualifications</span></h2><ul><li><p><span>A VLSI Design Engineer with extensive experience in backend design</span></p></li><li><p><span>B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background.</span></p></li><li><p><span>2+ years of hands-on experience in a relevant domain</span></p></li><li><p><span>Strong understanding of Place & Route flow<br /> </span></p></li></ul><h2><span>Preferred Qualifications</span></h2><ul><li><p><span>Deep understanding of Physical construction and Integration.</span></p></li><li><p><span>Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.</span></p></li><li><p><span>Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).</span></p></li><li><p><span>Ability to support technology adoption and new tool integration.</span></p></li><li><p><span>Great teammate, self-learner, and able to work independently.</span></p></li></ul><p></p><p>#li-as6</p><p></p><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><p></p>