Quest Global

Engineering services, digital transformation, asset management

Physical Design Lead Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-time$130.3k - $160k

About the Job

Requirements

A bachelor's degree or foreign equivalent in Electronics Engineering or a related field.
Five years of experience in the job offered or a related position.
Demonstrable knowledge of the full Place and Route design flow, including logical synthesis, static timing analysis, design for test, placement, clock tree synthesis, and physical verification.
Demonstrable knowledge of hardening high-speed, low-power CPU designs.
Demonstrable knowledge of designing large system-on-chip full-chip and block-level Place and Route using advanced process technologies, including process nodes of 3nm or below.
Demonstrable knowledge of high-speed interfaces at chip level.
Demonstrable knowledge of clock tree creation, including synchronization points, achieving low latency, and minimizing power.
Demonstrable knowledge of designing with multi-corner multi-mode timing constraints.
Demonstrable knowledge of static timing analysis.
Demonstrable knowledge of controlling timing budgets between blocks and the chip using timing models such as ETM and ILM.
Demonstrable knowledge of ECO environments for Place and Route tools to fix timing violations.
Willingness to travel to unanticipated client locations throughout the U.S., approximately 30%, as required.

Responsibilities

Implement complex designs in the physical design flow from netlist to GDSII.
Work on TSMC advanced process nodes of 3nm or below.
Perform floor-planning and clock tree synthesis, and use ICC2 and Innovus tools related to Cadence and Synopsys.
Optimize designs using multi-corner multi-mode timing constraints.
Fix setup, hold, transition, capacitance, crosstalk, and minimum pulse width violations, as well as signal electromigration issues; resolve congestion, shorts, and skew.
Work on high-speed, complex clock-structure designs with large numbers of memories and instances.
Use PrimeTime to check and debug timing.
Analyze floorplans to reduce congestion using advanced scripting techniques.
Generate robust clock trees by analyzing synchronization points and achieving low latency and minimal power.
Work on static timing analysis, logic equivalence checks, extraction, noise, and power.
Control timing budgets between blocks and the top-level chip using timing models such as ETM and ILM.
Build ECO environments for Place and Route tools to fix timing violations.
Perform power analysis and IR drop analysis to meet requirements.
Work on physical verification, design rule checking, layout versus schematic, antenna checks, electrical rule checks, and design for manufacturing.
Perform logic equivalence checks for pre- and post-Place and Route designs.

Job Requirements Company: Quest Global Services-N.A., Inc.Position Title: Physical Design Lead EngineerLocation: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated clientlocations throughout the U.S.Position Responsibilities: Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration)and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM. Build ECO environments for place and route tools to fix all timing violations. Work onPower Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification(PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical RuleCheck (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre-Post Place and Route design. Position Requirements: Bachelor’s degree (or foreign equivalent) in Electronics Engineering, or arelated field, PLUS five (5) years of experience in the job offered or a related position. Experiencemust include demonstrable knowledge of: The full Place & Route design flow incl. logicalsynthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed,low power CPU designs; design of large SOC full chip & block level P&R using advanceProcess technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level;clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicornermulti-mode timing constraints; STA; control of timing budget between blocks & chip usingtiming model such as ETM, ILM; ECO environments for place & route tools to fix timingviolations. Travel to unanticipated client locations throughout the U.S., approximately 30%, asrequired. May telecommute from any location within the U.S.Apply at careers.quest-global.com and reference Job Code 28290.0330Pay Range: $130,333 - $160,000Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.

About the Company

Quest Global

Engineering services, digital transformation, asset management

QuEST Global provides engineering and lifecycle services across aerospace, automotive, energy, healthcare, and transportation, focusing on digital transformation and asset management. It uses edge computing, cloud, AI/ML, and industrial IoT to deliver tailored engineering solutions through long-term partnerships, service contracts, project-based engagements, and strategic collaborations. It differentiates itself with a broad industry footprint, global delivery model, and emphasis on partnerships, talent development, and workplace culture. Its goal is to help clients improve operational efficiency and drive business growth by transforming engineering processes and assets with digital tools and data-driven management.

Company size: 10,001+
Company stage: Growth Equity (Venture Capital)
Total funding: $581M
Headquarters: Greenville, SC
Founded: 1997

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