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Positron

Memory-first AI inference silicon for LLMs

Director of Silicon Validation

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeAustin, TX, USA$200k - $350k

About the Job

Requirements

  • A degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12 or more years of experience in ASIC verification and/or silicon validation, including at least 5 years in a leadership role.
  • A proven track record taking multiple complex ASICs from verification planning through successful first silicon and production ramp.
  • Deep hands-on expertise in SystemVerilog, UVM, constrained-random verification, functional coverage, and assertion-based verification.
  • Demonstrated ownership of a hardware emulation platform such as Cadence Palladium, Siemens Veloce, or Synopsys ZeBu, including model build flows, capacity and partitioning, transactors, and co-emulation.
  • Experience leading post-silicon bring-up, including first power-on, boot, interface training, characterization, and silicon debug.
  • A strong understanding of high-speed interface and memory subsystem validation, including PCIe, LPDDR/HBM, SerDes, and coherent interconnect.
  • Working knowledge of design for test (DFT), automatic test pattern generation (ATPG), and memory built-in self-test (MBIST), and how test structures interact with verification and bring-up.
  • Experience defining verification sign-off criteria and presenting readiness data to executive stakeholders.

Responsibilities

  • Lead and grow three interlocking disciplines: pre-silicon design verification, hardware emulation, and post-silicon validation and bring-up.
  • Own the verification strategy, test plans, and coverage closure criteria that gate tape-out, and make the data-driven readiness recommendation to executive leadership.
  • Define what content runs where across simulation, emulation, FPGA prototyping, and silicon to maximize bug discovery per engineering day and per compute dollar.
  • Build and scale the emulation environment into the platform that enables firmware and software bring-up well ahead of first silicon.
  • Establish the post-silicon bring-up plan, lab infrastructure, and on-chip observability and debug strategy before tape-out, and lead the bring-up effort when silicon arrives.
  • Drive bug triage, root cause analysis, escape analysis, and errata management, and own the respin-versus-workaround recommendation.
  • Partner with design, DFT, physical design, firmware, and software teams so that verification intent, debug hooks, and test content are designed in rather than bolted on.
  • Own regression infrastructure, compute and license capacity planning, and continuous integration for verification and emulation workloads.
  • Manage relationships with EDA and emulation vendors, verification IP suppliers, and third-party IP providers.
  • Recruit, mentor, and develop a high-performing verification and validation organization across multiple sites.

Desired Qualifications

  • Experience verifying and validating AI/ML accelerators, high-performance computing (HPC), or data center silicon.
  • Firmware or embedded software bring-up experience, including booting a bootloader or Linux on emulation or first silicon.
  • Hands-on deployment of formal verification methodology alongside simulation-based verification.
  • Experience with Arm-based subsystems and coherent mesh interconnects.
  • Familiarity with virtual prototyping, performance validation, and correlating silicon results to pre-silicon models.
  • A track record building verification automation and applying AI-assisted tooling to verification and debug workflows.
  • Experience scaling a validation organization across multiple geographic sites.
  • A successful track record of technology development within a dynamic start-up environment.

About the Company

Positron

Memory-first AI inference silicon for LLMs

Positron develops memory-first AI inference silicon and systems to scale large-language-model serving. Its Atlas systems rely on commodity LPDDR5X memory rather than expensive HBM/CoWoS to boost bandwidth and capacity, enabling more efficient LLM deployment at hyperscale. The company’s next-generation Asimov silicon (tape-out planned for late 2026; production in 2027) pairs compute with very large memory per chip (roughly 288 GB to 2,304 GB) and is designed to be combined into Titan configurations (four to eight Asimov chips) for extremely large models and long context windows. Positron has already deployed Atlas systems in the cloud, including 50+ racks at Oracle Cloud Infrastructure and partnerships with Parasail, Jump Trading, and i3d.net. Its goal is to provide scalable, memory-rich AI inference hardware that lowers cost and increases throughput for serving large language models.

Company size
51-200
Company stage
Series C
Total funding
$1.2B
Headquarters
Reno, NV
Founded
2023

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