DFT Engineering Director - CPU Cores Design for Testability

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THE ROLE:

We are searching for a senior technical leader to help drive and develop the Design for Testability (DFT) execution and roadmap for future generations of AMD CPUs.  This leader will have a high visibility role in future industry-leading CPUs, from concept through production.  You will direct the activities of a talented and experienced multi-geography team.

This role requires a unique combination of technical expertise, vision, organizational leadership, and operational excellence.  You will help shape the future of AMD’s CPU portfolio while developing the next generation of engineering innovators and leaders.

THE PERSON:

You have strong people leadership and teamwork skills, combined with deep DFT technical expertise and management in a large-scale and complex development environment.

You are comfortable operating at executive, leadership, management, and technical levels, influencing organizational strategy, driving critical engineering decisions, mentoring leaders, and representing AMD's technology leadership internally and externally.

Experience with the x86 architecture is a plus.

KEY RESPONSIBILITIES

• Functional management of the DFT organization in a high-performance CPU Cores development team.
• Develop future DFT features in collaboration with teams and peers across multiple domestic and international sites
• Support and drive DFT in multiple programs across many generations of the AMD CPU roadmap
• Establish organizational priorities, operating mechanisms, and execution frameworks that enable predictable delivery of complex programs.
• Foster a culture centered on innovation, inclusion, technical excellence, accountability, and continuous improvement.
• Drive workforce planning, succession planning, leadership development, and organizational growth.

PREFERRED EXPERIENCE

• Extensive and Senior experience in DFT architecture, design, debug, and verification
• Several years of leadership experience in DFT architecture, design, debug, and verification
• Knowledge and expertise in JTAG, ATPG, Scan, MBIST, and LBIST
• Familiarity with industry standard DFT tools
• Familiarity and experience with pattern generation, deployment, and debug on ATE
• Experience in concept-to-production development support for DFT activities
• Experience with IP-level debug and verification
• Working knowledge of Verilog or System Verilog; System C and C++ a plus
• Familiarity with ICL/PDL
• Scripting language experience
• Experience integrating AI into the development environment.

ACADEMIC CREDENTIALS

• BSEE or higher in Electrical or Computer Engineering, MSEE preferred

LOCATION

Austin, TX, but can also support: Santa Clara, CA; FT. Collins CO; Boxborough, MA; Fishkill, NY

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.