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Rambus

Licenses high-speed chip-to-chip connectivity IP

SPE Analog Engineering

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-time

About the Job

Requirements

  • A Master of Science in Electrical Engineering or Ph.D. and 10 or more years of analog or mixed-signal circuit design experience.
  • Understanding of signal integrity/power integrity principles and their interaction with receiver front-end principles.
  • Strong written and verbal communication skills and the ability to work across multiple functional teams using good engineering practices.

Responsibilities

  • Own analog and mixed-signal designs at chip and block level, especially high-speed data receivers.
  • Architect, design, simulate, and characterize high-performance, low-power, high-speed circuits, including receivers, samplers, and signal-conditioning circuits.
  • Model chip and block designs at various levels of detail for design tradeoff analysis and voltage and timing budgeting.
  • Supervise analog layout engineering to ensure attention to detail in high-performance analog layout for critical input/output blocks.
  • Work with cross-functional teams across geographies and time zones to ensure engagement and execution.
  • Document designs, guide and debug post-silicon validation, and correlate silicon to simulation.
  • Supervise layout.

Desired Qualifications

  • Direct chip design experience in DDR interface design.
  • Experience with Verilog coding.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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