A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
At least 10 years of experience in SoC architecture, ASIC development, or complex semiconductor system design.
Strong understanding of modern SoC architectures and subsystem integration.
Experience with one or more of the following: CPU, GPU, or NPU architectures; NoC or interconnect architectures; cache coherency protocols (CHI, ACE, or CXL); high-speed interfaces (PCIe, UCIe, or Ethernet); memory systems (DDR5, LPDDR5X, or HBM); or power/performance optimization.
Strong knowledge of RTL development and verification methodologies.
Experience with architecture modeling and performance analysis tools.
Familiarity with firmware/software interaction in complex SoC systems.
Experience in system architecture definition, C/C++/SystemC modeling, performance analysis and simulation, RTL and microarchitecture, AMBA/AXI/CHI protocols, PCIe/CXL/UCIe, memory subsystem architecture, hardware/software co-design, and silicon bring-up and debugging.
The role requires on-site presence in the Sunnyvale office.
Responsibilities
Define top-level SoC architecture and subsystem partitioning for complex semiconductor products.
Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.
Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.
Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.
Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments.
Define memory hierarchy, NoC/interconnect strategy, coherency architecture, and cache structures.
Evaluate and integrate third-party IPs, including CPU, GPU, NPU, PCIe, DDR/LPDDR, Ethernet, multimedia, and security subsystems.
Work with verification teams to define architectural test plans and validation strategies.
Support silicon bring-up, debugging, performance tuning, and post-silicon optimization.
Contribute to long-term technology and product roadmap planning.
Desired Qualifications
Experience with AI accelerator, GPU, networking, RISC-V, or datacenter SoC architectures.
Experience with chiplet-based or multi-die architectures.
Familiarity with advanced process technologies and package integration.
Experience with emulation, FPGA prototyping, and system-level validation.
Knowledge of Linux drivers, runtime software, or system software architecture.
Prior technical leadership experience across cross-functional engineering teams.
Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
Be Fearless:Unmute yourself. Test boundaries and get proven right.
Remain Adaptable:Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego:Selflessly collaborate towards our shared purpose.
About the role:
We are looking for an experienced and highly motivatedLeadSoCArchitect to lead the architecture definition and technical direction for next-generation semiconductor products. The ideal candidate will have strongexpertisein complex SoC architecture development, performance modeling, subsystem integration, and cross-functional collaboration across hardware, software, and system teams.
This role involves defining scalable and high-performance architectures for advancedcomputeplatforms including AI, GPU, multimedia, networking,RISC-Vordatacenter-class SoCs.This is a tech lead role and requireson-site presence in our Sunnyvale office. The ideal candidate must be willing to be an individual contributor while leading others.
What you'll do:
Define top-level SoC architecture and subsystem partitioning for complex semiconductor products.
Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.
Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.
Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.
Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments.
Define memory hierarchy, NoC/interconnect strategy, coherency architecture, and cache structures.
Evaluate and integrate third-party IPs including CPU, GPU, NPU, PCIe, DDR/LPDDR, Ethernet, multimedia, and security subsystems.
Work closely with verification teams to define architectural test plans and validation strategies.
Support silicon bring-up, debug, performance tuning, and post-silicon optimization.
Contribute to long-term technology and product roadmap planning.
Required Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of experience in SoC architecture, ASIC development, or complex semiconductor system design.
Strong understanding of modern SoC architectures and subsystem integration.
Experience with one or more of the following:
CPU/GPU/NPU architectures
NoC/interconnect architectures
Cache coherency protocols (CHI/ACE/CXL)
High-speed interfaces (PCIe, UCIe, Ethernet)
Memory systems (DDR5, LPDDR5X, HBM)
Power/performance optimization
Strong knowledge of RTL development and verification methodologies.
Experience with architecture modeling and performance analysis tools.
Familiarity with firmware/software interaction in complex SoC systems.
Excellent problem-solving, communication, and leadership skills.
Preferred Qualifications
Experience with AI accelerator, GPU, networking, RISC-V or datacenter SoC architectures.
Experience with chiplet-based or multi-die architectures.
Familiarity with advanced process technologies and package integration.
Experience with emulation, FPGA prototyping, and system-level validation.
Knowledge of Linux drivers, runtime software, or system software architecture.
Prior technical leadership experience across cross-functional engineering teams.
Technical Skills
System architecture definition
C/C++/SystemC modeling
Performance analysis and simulation
RTL and microarchitecture understanding
AMBA/AXI/CHI protocols
PCIe/CXL/UCIe
Memory subsystem architecture
HW/SW co-design
Silicon bring-up and debugging
Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.