Design for Test SoC Lead

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DFT - SOC Lead

THE ROLE:

As a DFT Lead you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves working with design architecture, design DFT/DFX, design block owners and physical design teams with ATE manufacturing environment, silicon debug, product quality and test cost perspectives. The DFT Lead is expected to apply past technical knowledge, learn new cutting-edge technologies and collaborate with teams to arrive at best manufacturable solution. The DFT Lead will ensure that DFT implementation is completed by architecture design specifications. This is the role of overseeing early architecture design definition to successful silicon high-volume production.

THE PERSON:

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT Leads interact with many external teams and must confidently represent his/her organization.

KEY RESPONSIBILITIES:

• Manage DFT activities across architecture, design implementation, verification, and test implementation for new products.
• Work closely with design teams and make sure DFT structures are correctly implemented.
• Drive internal DFT teams to correctly implement and create test solutions
• Promote ATE & production test environment, test cost and test quality enhancements in future AMD products through DFT architecture definitions and specifications
• The role is in AMD global quality and operation organization driving best manufacturing test solution through early product definition and pre & post silicon activities
• Plan for diagnosability and yield improvement

PREFERRED EXPERIENCE:

• 15+ years of semiconductor industry experience
• Significant DFT engineering experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Strong MBIST knowledge
• Experience in PHY, high-speed IO, digital communication and functional test development
• Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
• Good understanding of Verilog, synthesis, physical implementation and STA
• Good understanding of verification methodology
• Knowledge of FPGA logic, synthesis and design flow is a plus
• Knowledge of embedded design and firmware methodology is a plus
• Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills and works well in a group environment that spans across continents

ACADEMIC CREDENTIALS:

• Bachelors or Masters Electrical/Electronics/Computer Engineering 

LOCATION:

Hyderabad/Bengaluru, India

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.