DV Lead Engineer

<strong>Job Requirements </strong><br><h3><strong>Job Description</strong></h3><p> </p><p><strong>Job Title:</strong> Senior Gate-Level Simulation (GLS) Verification Engineer</p><p><strong>Location:</strong> Bangalore, Karnataka, India</p><p><strong>Team:</strong> SoC Design Verification / Silicon Sign-off</p><p><strong>Position Summary</strong></p><p>We are seeking a highly skilled and meticulous Gate-Level Simulation (GLS) Verification Engineer to serve as the <strong>last line of defense before silicon tape-out</strong>. In this critical role, you will be responsible for verifying the post-synthesis, final netlist of our complex SoCs, ensuring that the design's functionality remains correct after synthesis, placement, and routing.</p><p>You will hunt down the most subtle and challenging bugs related to timing, power, and reset that are invisible at the RTL level. The ideal candidate is a tenacious debugger with a deep understanding of digital design, simulation technology, and the patience to navigate complex gate-level netlists.</p><p> </p><h3><strong>Key Responsibilities</strong></h3><p> </p><ul><li><strong>Own and execute the complete GLS verification strategy</strong> for complex IPs and full-chip SoCs, from initial planning to final sign-off.</li><li>Bring up, maintain, and debug existing UVM/SystemVerilog testbenches in both zero-delay and back-annotated (<strong>SDF</strong>) timing simulation environments.</li><li>Debug complex test failures in the gate-level netlist, identifying root causes related to:</li><li class="ql-indent-1"><strong>Timing-dependent race conditions</strong> and glitches.</li><li class="ql-indent-1"><strong>Reset propagation</strong> and synchronization issues.</li><li class="ql-indent-1"><strong>X-propagation</strong> bugs masked by optimistic RTL simulation.</li><li class="ql-indent-1">Initialization failures of flops and memories.</li><li>Develop and maintain robust automation scripts (<strong>Perl, Python, Shell</strong>) to manage GLS regressions, parse massive log files, and generate actionable reports.</li><li>Verify critical <strong>Design-for-Test (DFT)</strong> logic, including scan-chain integrity, memory BIST, and JTAG controllers, at the gate level.</li><li>Conduct <strong>power-aware GLS</strong> using UPF to validate low-power structures such as isolation cells, level shifters, and power-gating sequences.</li><li>Collaborate closely with RTL design, Physical Design (PD), and DFT teams to rapidly triage, root-cause, and resolve GLS failures.</li></ul><p> </p><h3><strong>Required Qualifications</strong></h3><p> </p><ul><li>Bachelor’s or Master’s degree in Electrical/Computer Engineering or a related field.</li><li><strong>8+ years of hands-on experience in ASIC verification, with a significant portion dedicated specifically to Gate-Level Simulation.</strong></li><li>Proven expertise in running and debugging simulations on EDA tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa.</li><li>Strong debugging skills using waveform viewers like Verdi or DVE, with the ability to trace signals through a gate-level netlist.</li><li>Excellent scripting skills in Perl or Python.</li><li>Solid understanding of the differences between RTL and GLS environments.</li></ul><br><br>