Senior Layout Design Engineer

Job Description and Requirements

Alternate Job Titles

• Sr Layout Design Engineer
• Sr IC Layout Engineer
• Sr Memory Layout Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years translating circuit concepts into physical silicon, and you understand that layout is not just about fitting shapes into a floorplan, it is about making decisions that affect performance, power, and manufacturability at every turn. A well-placed via or carefully routed power rail can mean the difference between a memory cell that works at corner conditions and one that fails in the field.

You are comfortable working in both the big picture and the microscopic detail. One day you are reviewing a full memory compiler layout strategy, the next you are debugging a DRC violation that traces back to a single polygon edge. You do not wait for someone to hand you a perfect spec. You ask the right questions, understand the tradeoffs, and move forward with what you know. You care about the craft and take pride in clean, efficient layouts that other engineers can build on. At Synopsys, you will work on Foundation IP that powers chips across the industry.

What You'll Be Doing

• Design and develop custom layouts for Embedded Memory IPs, Standard Cells, and IO structures using proficiency with Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, and Calibre DRC/LVS verification tools.
• Optimize layout topologies for density, performance, power, and manufacturability across advanced process nodes.
• Collaborate with circuit designers and verification teams to ensure layouts meet electrical and physical design requirements
• Debug and resolve DRC, LVS, and antenna violations in complex hierarchical designs
• Develop and refine layout methodologies and automation flows to improve efficiency across the IP portfolio
• Participate in design reviews and provide technical feedback on layout strategies
• Maintain documentation of layout guidelines, design decisions, and process updates

The Impact You Will Have

• Deliver high-performance, high-density memory layouts that enable customers to meet aggressive PPA targets
• Reduce time-to-market for Foundation IP products by improving layout development efficiency
• Enable successful tape-outs by catching and resolving physical design issues early
• Contribute to layout methodology improvements that scale across multiple process nodes. The team develops Foundation IP solutions across multiple advanced technology nodes.
• Support Synopsys' position as the leading provider of silicon-proven Foundation IP
• Help customers achieve first-pass silicon success with layouts that meet manufacturing requirements

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related field
• 2+ years of hands-on experience in custom IC layout design, with focus on memory compilers, standard cells, or analog/mixed-signal blocks
• Deep understanding of layout fundamentals including device matching, parasitic extraction, electromigration, and IR drop
• Proficiency with industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent
• Solid grasp of DRC/LVS verification flows and ability to debug complex rule violations
• Strong documentation and communication skills for cross-functional collaboration

Who You Are

• You approach layout as a craft and care about producing work that is clean, efficient, and maintainable
• You can explain a layout tradeoff to a circuit designer in two minutes and walk away with alignment
• You are detail-oriented without losing sight of the bigger picture
• You work well independently but know when to ask for input or flag potential issues early
• You stay current with layout techniques and actively look for ways to improve your methods

The Team You'll Be Part Of

You will join the Foundation IP team in Ho Chi Minh City, a group focused on designing and delivering high-performance silicon IP including logic libraries, memory compilers, and IO solutions. This team works closely with global Synopsys engineering teams and directly supports customers who depend on these IP blocks for their most critical chip designs.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.